To address the high cost

long testing cycle

and high risk associated with testing brushless DC motor(BLDC)drives

this paper proposes a motor simulator design scheme based on linear active disturbance rejection control(LADRC).The hardware of the simulator is first built using power electronic converters

and an outer speed control loop is introduced on top of the conventional single-loop current control to emulate the motor’s port electrical characteristics.To mitigate performance degradation caused by internal and external disturbances such as load changes and parameter variations

the conventional PI controller is replaced by the LADRC strategy.The core of this approach lies in employing a linear extended state sbserver(LESO)to estimate and compensate for the system’s “total disturbance” in real time

thereby enhancing system robustness.Comparative experiments conducted on an RT-BOX hardware-in-the-loop simulation platform demonstrate that the proposed LADRC strategy outperforms conventional PI control under disturbance conditions

showing stronger disturbance rejection

faster dynamic response

and higher control stability.The results verify the feasibility of the proposed motor simulator design and the superiority of the LADRC strategy

providing an effective solution for developing cost-efficient and reliable drive testing platforms.