This article discusses the architecture design of DMA controller on high performance GPS receiver based on RTEMS which achieves the optimal integration of DMA IP and navigation baseband system. The authors designed the hardware architecture of DMA IP and made full use of hardware performance with the idea of multiplexing

then used register and FIFO buffer to achieve read-write control. Furthermore

the researchers designed the DMA controller with Verilog HDL and verified the design on Altera Cyclone4 FPGA. The result demonstrates that DMA controller can ease the CPU’s burden and shorten the acquisition & tracking time which improves the performance of the whole system.