In view of the flaws of repeated and cumbersome communication process

inefficiency and small data throughput of the traditional dual-core control acquisition system of multi-lead EEG machine

it advances a high speed

multi-channel and real-time synchronous acquisition system

based on FPGA. The SDRAM is mainly controlled by FPGA which FIFO-internalizes the SDRAM via the program to achieve the asynchronous clock reading-while-writing of the SDRAM by the ping pong operation of two pairs of FIFO of SDRAM

which ensures the ongoing of interfaces data transmission between FPGA and ARM and efficient communication by concise and rigorous parallel interface agreements. The FPGA and SDRAM can be equivalent to a SDRAM which can automatically collect data. Tests show that this system avoids the repeated copy of transfer process and redundant complex data transfer operation

and improves the data throughput and transfer rate

which meets the requirement for the design indexes of 256-lead EEG machine with the sample frequency up to 20 kHz or even higher.