弱电网下基于频率自适应的新型锁相环设计方法及其稳定性分析

杨明; 宋静文; 刘子坤; 肖笛

doi:10.19783/j.cnki.pspc.251267

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弱电网下基于频率自适应的新型锁相环设计方法及其稳定性分析

应用研究 | 更新时间：2026-05-14

- 弱电网下基于频率自适应的新型锁相环设计方法及其稳定性分析
- Design and stability analysis of a new frequency-adaptive phase-locked loop for weak grids
- 电力系统保护与控制 2026年54卷第10期
- 作者机构：
  
  河南省煤矿装备智能检测与控制重点实验室 (河南理工大学电气工程与自动化学院),河南,焦作,454003
- 作者简介：
- 基金信息：
- DOI：10.19783/j.cnki.pspc.251267
  中图分类号：
- 纸质出版：2026
- 稿件说明：
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杨明, 宋静文, 刘子坤, 等. 弱电网下基于频率自适应的新型锁相环设计方法及其稳定性分析[J]. 电力系统保护与控制, 2026,54(10).

YANG Ming, SONG Jingwen, LIU Zikun, et al. Design and stability analysis of a new frequency-adaptive phase-locked loop for weak grids[J]. Power System Protection and Control, 2026, 54(10).
杨明, 宋静文, 刘子坤, 等. 弱电网下基于频率自适应的新型锁相环设计方法及其稳定性分析[J]. 电力系统保护与控制, 2026,54(10). DOI： 10.19783/j.cnki.pspc.251267.

YANG Ming, SONG Jingwen, LIU Zikun, et al. Design and stability analysis of a new frequency-adaptive phase-locked loop for weak grids[J]. Power System Protection and Control, 2026, 54(10). DOI： 10.19783/j.cnki.pspc.251267.

摘要

针对弱电网下锁相环与电网阻抗相互耦合而导致系统稳定性下降的问题，从优化锁相环控制结构的角度出发，提出一种具有频率自适应性的新型锁相环设计方法。首先，建立考虑锁相环影响的系统输出导纳模型，对传统锁相环 (phase-locked loop

PLL) 和解耦锁相环 (decoupled phase-locked loop

DPLL) 在弱电网下的稳定性与动态性能进行分析，可得传统 PLL 与 DPLL 在电网阻抗增大以及电网波动时均表现出稳定性下降与动态响应变差的特征。然后，在 DPLL 基础上引入惯性环节与外环频率跟踪单元，构建一种具有频率自适应的新型锁相环 (new phase-locked loop

NPLL) 结构，通过增强系统阻尼与实时频率追踪能力来优化控制性能。最后，仿真与实验结果表明，所提方案不仅显著拓宽了电网阻抗的适应范围，而且在电网波动的工况下表现出优于传统 PLL 与 DPLL 的频率跟踪能力与动态响应，有效提升了系统的鲁棒性与并网电能质量。

Abstract

To address the issue of decreased system stability caused by the coupling between the phase-locked loop (PLL) and grid impedance in weak grids

a novel frequency-adaptive PLL design method is proposed from the perspective of optimizing the control structure. First

a system output admittance model considering the influence of the PLL is established. Based on this model

the stability and dynamic performance of the conventional PLL and the decoupled phase-locked loop (DPLL) under weak grid conditions are analyzed. The results show that both PLL and DPLL exhibit reduced stability and degraded dynamic response as grid impedance increases or grid fluctuations intensify. Then

based on the DPLL

an inertial element and an outer-loop frequency tracking unit are introduced to construct a new frequency-adaptive phase-locked loop (NPLL) structure with frequency adaptability. By enhancing system damping and real-time frequency tracking capability

the proposed method improves overall control performance. Finally

simulation and experimental results demonstrate that the proposed scheme significantly expands the range of grid impedance adaptability and exhibits superior frequency tracking capability and dynamic response under grid fluctuation conditions compared to traditional PLL and DPLL

thereby effectively improving system robustness and grid-connected power quality.

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references

XU H, YU C, SU J, et al. Impedance model-based stability analysis of single-stage grid-connected inverters considering PV panel characteristics and DC-side voltage[J]. Protection and Control of Modern Power Systems, 2025, 10(4): 130-145.

FANG Tianzhi, LIU Hao, ZHANG Huili, et al. Robust technique using the optimized grid voltage feedforward to conquer the impact induced by dual factors for grid-connected inverter in weak grid[J]. IEEE Transactions on Industrial Electronics, 2024, 71(7): 7199-7209.

WEN B, BOROYEVICH D, BURGOS R, et al. Analysis of D-Q small-signal impedance of grid-tied inverters[J]. IEEE Transactions on Power Electronics, 2016, 31(1): 675-687.

BAO Chenlei, RUAN Xinbo, WANG Xuehua, et al. Step-by-step controller design for LCL-type grid-connected inverter with capacitor-current-feedback active-damping[J]. IEEE Transactions on Power Electronics, 2014, 29(3): 1239-1253.

YANG Dongsheng, WANG Xiongfei, LIU Fangcheng, et al. Symmetrical PLL for SISO impedance modeling and enhanced stability in weak grids[J]. IEEE Transactions on Power Electronics, 2020, 35(2): 1473-1783.

XU J, QIAN H, QIAN Q, et al. Modeling, stability, and design of the single-phase SOGI-based phase-locked loop considering the frequency feedback loop effect[J]. IEEE Transactions on Power Electronics, 2023, 38(1): 987-1002.

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