Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems

Qingyi Wang; Binlei Ju; Yudi Lei; Dan Zhou; Shuai Yin; Danyun Li

doi:10.17775/CSEEJPES.2021.01560

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Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems

Regular Papers | 更新时间：2026-10-15

- Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems
- Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems
- 中国电机工程学会电力与能源系统学报(英文) 2023年9卷第5期页码：1720-1731
- 作者机构：
  
  Hubei Key Laboratory of Advanced Control and Intelligent Automation for Complex Systems, School of Automation, China University of Geosciences,Wuhan,China
- 作者简介：
- 基金信息：
- DOI：10.17775/CSEEJPES.2021.01560
  中图分类号：
- 纸质出版：2023-09-01
- 稿件说明：
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Qingyi Wang, Binlei Ju, Yudi Lei, 等. Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems[J]. 中国电机工程学会电力与能源系统学报(英文), 2023,9(5):1720-1731.

Qingyi Wang, Binlei Ju, Yudi Lei, et al. Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems[J]. CSEE Journal of Power and Energy Systems, 2023, 9(5): 1720-1731.
Qingyi Wang, Binlei Ju, Yudi Lei, 等. Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems[J]. 中国电机工程学会电力与能源系统学报(英文), 2023,9(5):1720-1731. DOI： 10.17775/CSEEJPES.2021.01560.

Qingyi Wang, Binlei Ju, Yudi Lei, et al. Design and Hardware-in-the-loop Validation: A Fractional Full Feed-forward Method for Grid Voltage in LCL Grid-connected Inverter Systems[J]. CSEE Journal of Power and Energy Systems, 2023, 9(5): 1720-1731. DOI： 10.17775/CSEEJPES.2021.01560.

摘要

Abstract

The harmonic disturbance in the background grid is a problem that must be considered in the design of a grid-connected inverter. However

the full feed-forward method cannot completely suppress the harmonic disturbance in theory and is sensitive to noise. To tackle these problems

a fractional full feed-forward method of grid voltage is proposed in this paper. First

the mathematical model of the full feed-forward method is deduced

and the differences with the theoretical solution

which can suppress all harmonics

are analyzed. Then

the parameter equation

the harmonic suppression performance

stability analysis and the implementation process of this method are given. Compared with the full feed-forward method

the proposed method not only further improves the harmonic suppression performance

but also reduces the order of the mathematical model of the differential term in the feed-forward loop. In addition

the proposed method can be used to flexibly design feed-forward coefficients by selecting the order of suppressed harmonics. Finally

the proposed method is validated by a hardware-in-the-loop experiment on a MT real-time control platform NI PXIE-1071.

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