The composition and operation control methods of distribution networks with large-scale distributed photovoltaic generation are undergoing significant changes

which pose new demands on distribution network measurement techniques. Synchronized phasor measurement in distribution networks not only enables comprehensive observability of the distribution network but also provides a data foundation for control and protection applications. However

compared to the power transmission network

the distribution network has complex electrical quantities and high requirements for measurement points

which pose new demands for phasor measurement methods and the hardware form of the devices. Therefore

this paper proposes a low-latency phasor measurement algorithm suitable for chip integration and has conducted experiments on an FPGA. This approach introduces an FPGA-based hardware architecture for distribution-side PMU

analyzes the delay requirements for the passband and stopband of filters in synchronized phasor measurement

and proposes a low-latency phasor algorithm based on nonlinear phase filters. A nonlinear error mathematical model for passband gain and stopband attenuation has been established

and a low-latency FIR filter has been optimized and designed. A low-latency phasor algorithm suitable for chip integration has been proposed. Furthermore

the algorithm has been subjected to simulation testing and experimental validation. Simulation tests and FPGA experiments demonstrate that the proposed algorithm

while ensuring accuracy above the PMU standard requirements

effectively reduces the computational response time. This can provide a fast and reliable data foundation for the protection and control of distribution networks and lays a theoretical research foundation for the practical application of chip-based devices.