This paper systematically studies the parallel current balancing method of SiC MOSFET

focusing on the problem of imbalanced parallel current distribution of SiC MOSFET. First

the static parameters of 30 SiC MOSFET devices are statistically analyzed. Then

the Pearson correlation coefficient between chip gate-source voltage and transconductance at different current levels is established

and the gate-source voltage corresponding to a correlation coefficient of 0.7 is defined as the current sharing voltage. The principle of adopting the current sharing voltage as the chip sorting parameter is proposed. Secondly

a parallel current balancing method of SiC MOSFET in different layouts is proposed based on current sharing voltage sorting. Finally

an experimental platform is built to verify the effectiveness of the proposed method for both parallel connection of multiple discrete devices and multi-chip parallel power modules. Experimental results show that the chip parameter sorting method can not only reduce the imbalanced current between parallel chips in symmetrical layout

but also use chip parameter variation to quantitatively compensate for the current imbalance caused by parasitic parameter mismatch when the circuit is asymmetric.