CHEN Jianchang, XU Jianzhong, LIU Yifan, et al. FPGA Parallel Simulation Method for Power Generation Units in Doubly-fed Wind Farms[J]. 2026, 46(4): 1582-1591.
CHEN Jianchang, XU Jianzhong, LIU Yifan, et al. FPGA Parallel Simulation Method for Power Generation Units in Doubly-fed Wind Farms[J]. 2026, 46(4): 1582-1591. DOI: 10.13334/j.0258-8013.pcsee.250309.
大规模双馈风电场作为实现我国“双碳”目标的陆上风电主力,其高比例电力电子设备的接入对电力系统电磁暂态高精度仿真技术提出日益严苛的要求,面向上百台发电单元的双馈场站全拓扑精细化微秒级仿真研究仍相对空白。基于现场可编程门阵列(field programmable gate array,FPGA)微秒级小步长并行仿真能力,提出一种面向双馈风电场站的发电单元FPGA并行仿真方法。首先,进行双馈感应电机微秒级高并行度离散化建模与换流器受控源建模;接着,对节点导纳矩阵分块降维以实现发电单元内部分网并行,并从整体电路解算层面提出单元级并行仿真框架;最后,考虑实时数字仿真器(real time digital simulator,RTDS)与FPGA仿真平台特点,分配发电单元的微秒级小步长仿真任务并搭建联合仿真硬件框架;通过对比RTDS标准模型与RTDS+ FPGA联合仿真模型,验证所提并行仿真方法的准确性。
Abstract
As a dominant form of onshore wind power supporting China’s twin goals of carbon peak and carbon neutrality goals
large-scale doubly-fed induction generator (DFIG) wind farms with high-penetration power electronic devices impose increasingly stringent requirements on electromagnetic transient simulation technologies for power systems. However
research on full-topology refined microsecond-level simulation for DFIG-based wind farms with hundreds of generation units remains relatively scarce. This paper proposes a parallel simulation methodology for DFIG wind farm clusters based on field programmable gate array (FPGA)
utilizing their microsecond-level small time-step computation capability. Firstly
a microsecond-level highly parallel discrete model is established for doubly-fed induction machines
accompanied by controlled-source modeling development for power converters. Subsequently
the nodal admittance matrix is partitioned and reduced in dimension to achieve internal network parallelism within the power generation unit
and a unit-level parallel simulation framework is simultaneously constructed at the global circuit-solving level. Finally
considering the characteristics of real time digital simulator (RTDS) and FPGA platforms
microsecond-level small-step simulation tasks are allocated for generation units while establishing a co-simulation hardware architecture through platform- optimized task distribution. Through comparative analysis between RTDS benchmark models and RTDS+FPGA co-simulation models
the accuracy of the proposed parallel simulation method is systematically validated.