基于RISC-V处理器的认证加密紧耦合芯片设计

方炜楷; 詹瑞典; 蔡述庭; 熊晓明

doi:10.12052/gdutxb.250044

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基于RISC-V处理器的认证加密紧耦合芯片设计

集成电路科学与工程 | 更新时间：2026-05-27

- 基于RISC-V处理器的认证加密紧耦合芯片设计
- A Design of Tightly Coupled Chip for Authentication Encryption Based on RISC-V Processor
- 广东工业大学学报 2025年42卷第6期页码：12-17
- 作者机构：
  
  广东工业大学集成电路学院,广东,广州,510006
- 作者简介：
  
  方炜楷(1999–) ，男，硕士研究生，主要研究方向为数字集成电路设计，E-mail: 2112202083@mail2.gdut.edu.cn
  蔡述庭(1979–) ，男，教授，博士，主要研究方向为超大规模集成电路设计等，E-mail: shutingcai@gdut.edu.cn
- 基金信息：
  
  广东省重点领域研发计划项目(2022B0701180001)
- DOI：10.12052/gdutxb.250044
  中图分类号： TN402
- 纸质出版：2025
- 稿件说明：
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方炜楷, 詹瑞典, 蔡述庭, 等. 基于RISC-V处理器的认证加密紧耦合芯片设计[J]. 广东工业大学学报, 2025, 42(6): 12–17.

Fang Weikai, Zhan Ruidian, Cai Shuting, et al. A Design of Tightly Coupled Chip for Authentication Encryption Based on RISC-V Processor[J]. 2025, 42(6): 12-17.
方炜楷, 詹瑞典, 蔡述庭, 等. 基于RISC-V处理器的认证加密紧耦合芯片设计[J]. 广东工业大学学报, 2025, 42(6): 12–17. DOI： 10.12052/gdutxb.250044

Fang Weikai, Zhan Ruidian, Cai Shuting, et al. A Design of Tightly Coupled Chip for Authentication Encryption Based on RISC-V Processor[J]. 2025, 42(6): 12-17. DOI： 10.12052/gdutxb.250044.

摘要

随着物联网技术的快速普及，资源受限环境下高效的数据加密成为制约其进一步发展的关键问题。传统加密算法难以在低硬件资源消耗下同时兼顾数据机密性与完整性，而认证加密技术通过以最小计算和内存开销提供强安全性保障，成为适用于低面积设备的高效解决方案。因此，本文将RISC-V架构的灵活性与认证加密算法的高效性相结合，提出了一个集成认证算法的安全内核，通过将RISC-V内核通用寄存器与专用计算模块紧耦合，并扩展指令实现硬件加速，提高物联网设备数据的高效防护能力。实验表明，与传统协处理器方案相比，本设计逻辑资源消耗降低了约60%，同时节省了所有额外的寄存器资源；与纯软件实现相比提供了约150倍的加速效果。所提出的核心模块可为其他具有相同底层算子算法提供等效加速，具有显著灵活性。本文为现代物联网设备提供了一种高效可扩展的加密解决方案。

Abstract

With the rapid proliferation of Internet of Things (IoT) technology

efficient data encryption in resource-constrained environments has become a critical issue hindering further development. Traditional encryption algorithms struggle to balance data confidentiality and integrity at low hardware resource consumption. In contrast

authenticated encryption techniques offer a robust security guarantee with minimal computational and memory overhead

making them an efficient solution for low-cost devices. This paper combines the flexibility of the RISC-V architecture with the efficiency of authenticated encryption algorithms

proposing a secure kernel that integrates authentication algorithms. This kernel tightly couples the general-purpose registers of the RISC-V core with dedicated computational modules

utilizing extended instructions for hardware acceleration to enhance the effective protection of data in IoT devices. Experimental results indicate that

compared with traditional coprocessor solutions

this design reduces logical resource consumption by approximately 60% while saving all additional register resources. Additionally

it provides about a 150-fold acceleration compared with pure software implementations. The proposed core module can deliver equivalent acceleration for other algorithms with similar underlying operators

demonstrating significant flexibility. This research offers an efficient and scalable encryption solution for modern IoT devices.

关键词

Keywords

references

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