高性能模数转换器技术研究进展

王振宇; 谢欢林; 田家炜; 简明朝; 陈豪; 杨嘉俊; 李明杰; 郭春炳

doi:10.12052/gdutxb.240145

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高性能模数转换器技术研究进展

集成电路科学与工程 | 更新时间：2026-05-27

- 高性能模数转换器技术研究进展
- An Overview of High Performance Analog-to-Digital Converters
- 广东工业大学学报 2024年41卷第6期页码：1-19
- 作者机构：
  
  1. 广东工业大学信息工程学院,广东,广州,510006
  2. 广东工业大学集成电路学院,广东,广州,510006
- 作者简介：
  
  王振宇(2000–) ，男，硕士研究生，主要研究方向为模数转换器设计，E-mail：sydwzy@foxmail.com
  郭春炳(1971–) ，男，教授，博士，主要研究方向为模数混合集成电路设计，E-mail：cbguo@gdut.edu.cn
- 基金信息：
  
  广东省重点领域研发计划项目(2018B010115002)
- DOI：10.12052/gdutxb.240145
  中图分类号： TN792
- 纸质出版：2024
- 稿件说明：
移动端阅览
王振宇, 谢欢林, 田家炜, 简明朝, 陈豪, 杨嘉俊, 李明杰, 郭春炳. 高性能模数转换器技术研究进展[J]. 广东工业大学学报, 2024, 41(6): 1-19.

Wang Zhen-yu, Xie Huan-lin, Tian Jia-wei, et al. An Overview of High Performance Analog-to-Digital Converters[J]. 2024, 41(6): 1-19.
王振宇, 谢欢林, 田家炜, 简明朝, 陈豪, 杨嘉俊, 李明杰, 郭春炳. 高性能模数转换器技术研究进展[J]. 广东工业大学学报, 2024, 41(6): 1-19. DOI： 10.12052/gdutxb.240145.

Wang Zhen-yu, Xie Huan-lin, Tian Jia-wei, et al. An Overview of High Performance Analog-to-Digital Converters[J]. 2024, 41(6): 1-19. DOI： 10.12052/gdutxb.240145.

摘要

模拟/数字数据转换器(Analog-to-Digital Converter

ADC)是连接模拟世界与数字世界的桥梁，随着设计技术和制造工艺的发展，其各项性能指标有了长足的进步。本文首先介绍ADC的分类和性能特点，随后从高速ADC和高精度ADC两个设计方向，阐述不同结构ADC的基本原理和技术发展。在高速ADC方向，本文聚焦于SAR ADC和Pipelined SAR ADC的性能优化技术，如CDAC控制方法和比较器设计、非二进制冗余、环路展开以及级间冗余等。在高精度ADC方向，本文分析了Delta-Sigma ADC的多种类型和优缺点，并介绍了Zoom ADC、NS-SAR ADC的技术特点。本文还总结了一些新型的混合架构ADC，介绍它们的组成和研究进展。

Abstract

Analog-to-Digital Converter (ADC) is the bridge connecting the analog world and the digital world. With the development of circuit techniques and manufacturing process

its performance indicators have made great progress. The classification and performance characteristics of ADCs are firstly introduced

and then a description is made on the basic principles and technological development of ADCs of different structures including directions: high-speed and high-resolution ADCs. For high-speed ADCs

this article focuses on performance optimization techniques for SAR ADCs and Pipelined-SAR ADCs

such as CDAC controlling methods and comparator design

non-binary redundancy

loop-unrolled

and inter-stage redundancy. For high-resolution ADCs

the various types of Delta-Sigma ADCs and their advantages are analyzed

and the technical characteristics of Zoom ADCs and NS-SAR ADCs introduced. Some new types of hybrid-architecture ADCs are also summarized

describing their composition and research progress.

关键词

Keywords

references

张军, 何方, 徐海宁, 等. 高性能音频模数转换器TLV320ADC6140的应用技术研究[J]. 电子世界, 2020(15): 31-33.

EUN J P , HA Y H , KYOON D J. A 0.4-to-1 V voltage scalable Delta Sigma ADC with two-step hybrid integrator for iot sensor applications in 65-nm LP CMOS[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2017, 64(12): 1417-1421

GUO Z J, SU C X, XU R M, et al . Column level ADC design method of CMOS image sensor based on coarse and fine quantization parallel and TDC hybrid[J ] . Acta Electronica Sinica, 2024, 52(2): 486-499.

LIU J, LUO Z, XIONG X. Low-resolution ADCs for wireless communication: a comprehensive survey[J]. IEEE Access, 2019, 7: 91291-91324.

HUA Y, FENG W, CAO J C. Advancements in terahertz communication circuits for 6G technology vision[J]. Mobile Communications, 2023, 47(5): 7-13.

NYQUIST H. Certain topics in telegraph transmission theory[J]. Transactions of the American Institute of Electrical Engineers, 1928, 47(2): 617-644.

MALOBERTI F. Data converters specifications[M]. Berlin: Springer, 2007.

朱樟明, 杨银堂. 低功耗CMOS逐次逼近型模数转换器[M]. 北京: 科学出版社, 2015.

PAVAN S, SCHREIER R, TEMES G C. Understanding delta-sigma data converters[M]. Hoboken, NJ, USA: Wiley, 2017.

PETERSON J G. A monolithic video A/D converter[J]. IEEE Journal of Solid-State Circuits, 1979, 14(6): 932-937.

LEWIS S H, GRAY P R. A pipelined 5-Msample/s 9 bit analog-to-digital converter[J]. IEEE Journal of Solid-State Circuits, 1987, 22(6): 954-961.

LI J, MALOBERTI F. Pipeline of successive approximation converters with optimum power merit factor[C]//9th International Conference on Electronics, Circuits and Systems. Dubrovnik: IEEE, 2002, 1: 17-20.

CHAE Y, SOURI K, MAKINWA K A A. A 6.3 µW 20 bit incremental zoom-ADC with 6 ppm INL and 1 µV offset[J]. IEEE Journal of Solid-State Circuits, 2013, 48(12): 3019-3027.

FREDENBURG J A, FLYNN M P. A 90-MS/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC[J]. IEEE Journal of Solid-State Circuits, 2012, 47(12): 2898-2904.

RABII S, WOOLEY B A. A 1.8-V digital-audio sigma-delta modulator in 0.8-µm CMOS[J]. IEEE Journal of Solid-State Circuits, 1997, 32(6): 783-796.

ELAND E, KARMAKAR S, GÖNEN B, et al . A 440-µW, 109.8-dB DR, 106.5-dB SNDR discrete-time zoom ADC with a 20-kHz BW[J ] . IEEE Journal of Solid-State Circuits, 2021, 56(4): 1207-1215.

ZHANG Y, QIAO D. Energy efficiency of indoor THz communication systems with finite bit DACs/ADCs under minimum rate constraints[C]//2022 IEEE/CIC International Conference on Communications in China (ICCC). Sanshui: IEEE, 2022: 1044-1049.

ALI A M A. High speed data converters[M]. London: Institution of Engineering and Technology, 2016.

TANG X, LIU J, SHEN Y, et al . Low-power SAR ADC design: overview and survey of state-of-the-art techniques[J ] . IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(6): 2249-2262.

MCCREARY J L, GRAY P R. All-MOS charge redistribution analog-to-digital conversion techniques. I[J]. IEEE Journal of Solid-State Circuits, 1975, 10(6): 371-379.

LIU W, GUO S S, SHANG S G. Design of SAR-ADC with digital self-calibration for CZT detectors front-ends[J]. Journal of Electronic Measurement and Instrumentation, 2022, 36(9): 167-173.

ZHOU Y, XU B, CHIU Y. A 12-b 1-GS/s 31.5-mW time-interleaved SAR ADC with analog HPF-assisted skew calibration and randomly sampling reference ADC[J]. IEEE Journal of Solid-State Circuits, 2019, 54(8): 2207-2218.

HASSAN A W, ZHOU D, SILVA-MARTINEZ J. Matrix-based digital calibration technique for high-performance SAR and pipeline ADCs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, 71(1): 20-28.

WEI H, CHAN C H, CHIO U F, et al . An 8-b 400-MS/s 2-b-per-cycle SAR ADC with resistive DAC[J ] . IEEE Journal of Solid-State Circuits, 2012, 47(11): 2763-2772.

FURUTA M, NOZAWA M, ITAKURA T. A 10 bit, 40-MS/s, 1.21 mW pipelined SAR ADC using single-ended 1.5 bit/cycle conversion technique[J]. IEEE Journal of Solid-state Circuits, 2011, 46(6): 1360-1370.

LIU C C, CHANG S J, HUANG G Y, et al . A 10 bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure[J ] . IEEE Journal of Solid-State Circuits, 2010, 45(4): 731-740.

GINSBURG B P, CHANDRAKASAN A P. 500-MS/s 5 bit ADC in 65-nm CMOS with split capacitor array DAC[J]. IEEE Journal of Solid-State Circuits, 2007, 42(4): 739-747.

ZHU Y, CHAN C H, CHIO U F, et al . A 10 bit 100-MS/s reference-free SAR ADC in 90 nm CMOS[J ] . IEEE Journal of Solid-State circuits, 2010, 45(6): 1111-1121.

JIAN M C, ZHENG J W, KONG X J, et al . A 12 bit SAR ADC with a reversible VCM-based capacitor switching scheme[J ] . Microelectronics Journal, 2022, 129: 105588.

RAZAVI B. The StrongARM latch[J]. IEEE Solid-State Circuits Magazine, 2015, 7(2): 12-17.

SCHINKEL D, MENSINK E, KLUMPERINK E, et al . A double-tail latch-type voltage sense amplifier with 18ps setup+hold time[C ] //2007 IEEE International Solid-state Circuits Conference. Digest of technical papers. San Francisco: IEEE, 2007: 314-605.

BINDRA H S, LOKIN C E, SCHINKEL D, et al . A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise[J ] . IEEE Journal of Solid-State Circuits, 2018, 53(7): 1902-1912.

YANG D W, ZHANG C H, GUO C B. Design of a dynamic comparator circuit for ultra-low input common-mode voltage[J]. Application of Electronic Technique, 2021, 47(10): 48-52.

简明朝, 张春华, 符业聪, 等. 一种低功耗动态比较器: CN116488622B[P]. 2024-02-02.

HSIEH S E, KAO C C, HSIEH C C. A 0.5-V 12 bit SAR ADC using adaptive time-domain comparator with noise optimization[J]. IEEE Journal Solid-State Circuits, 2018, 53(10): 2763-2771.

LEE S K, PARK S J, PARK H J, et al . A 21 fJ/conversion-step 100 kS/s 10 bit ADC with a low-noise time-domain comparator for low-power sensor interface[J ] . IEEE Journal of Solid-State Circuits, 2011, 46(3): 651-659.

CHEN S W M, BRODERSEN R W. A 6 bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-µm CMOS[J]. IEEE Journal of Solid-State Circuits, 2006, 41(12): 2669-2680.

KUTTNER F. A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13 µm CMOS[C]//2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No. 02CH37315). San Francisco: IEEE, 2002: 176-177.

KIRAN S, CAI S, LUO Y, et al . A 52-Gb/s ADC-based PAM-4 receiver with comparator-assisted 2 bit/stage SAR ADC and partially unrolled DFE in 65-nm CMOS[J ] . IEEE Journal of Solid-State Circuits, 2018, 54(3): 659-671.

LIU Y H, CAO X D, ZHANG X L, et al . Design of integer-weight-based non-binary SAR ADC and calibration algorithm[J ] . Journal of Beijing Jiaotong University, 2022(2): 46.

CHEN X Q, YE F. Calibration for capacitor weight error of non-binary SAR ADC[J]. Computer Engineering and Design, 2018, 39(6): 7.

CAO Z, YAN S, LI Y. A 32 mW 1.25 GS/s 6b 2b/step SAR ADC in 0.13 µm CMOS[J]. IEEE Journal Solid-State Circuits, 2009, 44(3): 862-873.

KULL L, TOIFL T, SCHMATZ M, et al . A 3.1 mW 8b 1.2 GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32 nm digital SOI CMOS[J ] . IEEE Journal of Solid-State Circuits, 2013, 48(12): 3049-3058.

JIANG T, LIU W, ZHONG F Y, et al . Single-channel, 1.25-GS/s, 6 bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS[C ] //IEEE Custom Integrated Circuits Conference 2010. San Jose: IEEE, 2010: 1-4.

LIU S, RABUSKE T, PARAMESH J, et al . Analysis and background self-calibration of comparator offset in loop-unrolled SAR ADCs[J ] . IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 65(2): 458-470.

LEE E, PYO C, LEE S, et al . A 1.5-GS/s 6 bit single-channel loop-unrolled SAR ADC with speculative CDAC switching control technique in 28-nm CMOS[J ] . IEEE Transactions on Circuits and Syste ms I: Regular Papers, 2022, 69(10): 3954-3964.

BUHR S, MATTHUS C D, KHAFAJI M M, et al . A 1.38-mW 7 bit 1.7-GS/s single-channel loop-unrolled SAR ADC in 22-nm FD-SOI with 8.85 fJ/Conv. -step for GHz mobile communication and radar systems[J ] . IEEE Transactions on Microwave Theory and Techniques, 2023, 71(9): 3841-3851.

OH D R, MOON K J, LIM W M, et al . An 8 bit 1-GS/s asynchronous loop-unrolled SAR-flash ADC with complementary dynamic amplifiers in 28-nm CMOS[J ] . IEEE Journal of Solid-State Circuits, 2020, 56(4): 1216-1226.

GUO Z J, WANG Y L, XU R M, et al . High-speed fully differential two-step ADC design method for CMOS image sensor[J ] . Journal of Electronics Information Technology, 2023, 45(9): 3410-3419.

LU X M, HOU W J, XIE L X. Design of a 10 bit 280 ns conversion time two-stage pipelined cyclic ADC[J]. Research Progress of SSE, 2020, 40(5): 378-383.

WU C, YUAN J. A 12 bit, 300-MS/s single-channel pipelined-SAR ADC with an open-loop MDAC[J]. IEEE Journal of Solid-State Circuits, 2019, 54(5): 1446-1454.

FU Y, JIAN M, ZHENG J, et al . A 100ms/s 12 bit SAR-assisted pipeline ADC with gain-enhanced fully differential ring amplifier[C ] //2023 IEEE MTT-S International Wireless Symposium (IWS). Qingdao: IEEE, 2023: 1-3.

GUO X, CHEN R, CHEN Z, et al . A 13b 600-675MS/s tri-state pipelined-SAR adc with inverter-based open-loop residue amplifier[J ] . IEEE Journal of Solid-State Circuits, 2022, 58(3): 624-633.

KWON Y, KIM T, SUN N, et al . A 348-µW 68.8-dB SNDR 20-MS/s pipelined SAR ADC with a closed-loop two-stage dynamic amplifier[J ] . IEEE Solid-State Circuits Letters, 2021, 4: 166-169.

LI S M. Low power consumption Pipelined SAR ADC based on a novel ring amplifier[J]. China lntegrated Circuit, 2024, 33(5): 50-56.

ZHAO H, DAI F F. A 12 bit 260-MS/s pipelined-SAR ADC with ring-TDC-based fine quantizer for automatic cross-domain scale alignment[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10): 2883-2896.

RAZAVI B. The delta-sigma modulator[J]. IEEE Solid State Circuits Mag., 2016, 8(2): 10-15.

VERREAULT A, CICEK P V, ROBICHAUD A. oversampling ADC: a review of recent design trends[J]. IEEE Access, 2024, 12: 121753-121779.

WANG G F, LI K, LIU B, et al . A new high-precision Sigma_Delta modulator structure[J ] . Electronic Measurement Technology, 2022, 45(12): 1-5.

KARMAKAR S, GÖNEN B, SEBASTIANO F, et al . A 280 µW dynamic zoom ADC with 120 dB DR and 118 dB SNDR in 1 kHz BW[J ] . IEEE Journal of Solid-State Circuits, 2018, 53(12): 3497-3507.

ROH J, BYUN S, CHOI Y, et al . A 0.9-V 60-μW 1 bit fourth-order delta-sigma modulator with 83-dB dynamic range[J ] . IEEE Journal of Solid-State Circuits, 2008, 43(2): 361-370.

HAYASHI T, INABE Y, UCHIMURA K, et al . A multistage delta-sigma modulator without double integration loop[C ] //1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Anaheim: IEEE, 1986: 182-183.

FUKAZAWA M, OSHIMA T, FUJIWARA M, et al . A CT 2-2 MASH ΔΣ ADC with multi-rate LMS-based background calibration and input-insensitive quantization-error extraction[J ] . IEEE Journal of Solid-State Circuits, 2021, 56(10): 2943-2955.

HUANG J S, KUO S C, CHEN C H. A multistep multistage fifth-order incremental delta sigma analog-to-digital converter for sensor interfaces[J]. IEEE Journal of Solid-State Circuits, 2023, 58(10): 2733-2744.

PENG L X, WANG D, LI Z T, et al . A MASH structure interstage op-amp sharing Σ-Δ modulator[J ] . Microelectronics, 2024, 54(1): 38-44.

MAGHARI N, KWON S, MOON U K. 74 dB SNDR multi-loop sturdy-mash delta-sigma modulator using 35 dB open-loop opamp gain[J]. IEEE Journal of Solid-State Circuits, 2009, 44(8): 2212-2221.

TAN G, TAN G, QIN X, LIU Y, et al . A 10 MHz-BW 85 dB-DR CT 0-4 mash delta-sigma modulator achieving +5 dBFS MSA[J ] . IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12): 4781-4792.

CHAE Y, HAN G. Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator[J]. IEEE Journal of Solid-State Circuits, 2009, 44(2): 458-472.

ZHANG C, JIAN M, YUAN M, et al . A Σ-Δ modulator based on an inverter-based integrator with dynamic current switch[J ] . Journal of Physics: Conference Series, 2023, 2477(1): 012086.

MENG L, HU Y, ZHAO Y, et al . A 1.2-V 2.87-µW 94.0-dB SNDR discrete-time 2-0 MASH delta-sigma ADC[J ] . IEEE Journal of Solid-State Circuits, 2022, 58(6): 1636-1645.

RAZAVI B. The bootstrapped switch[J]. IEEE Solid-State Circuits Magazine, 2015, 7(3): 12-15.

高钧达, 郭春炳, 陆维立, 等. 一种具有低导通电阻的高速自举开关: CN113098455B[P]. 2022-05-10.

LIU X W, LIU Y T, JIANG Y M, et al . System level design and anaysis of fourth-order sigma-delta micromachined accelerometer[J ] . Journal of Harbin Institute of Technology, 2011, 43(7): 38-41.

JIANG D, SIN S W, QI L, et al . Recent advances in high-resolution hybrid discrete-time noise-shaping ADCs[J ] . IEEE Open Journal of the Solid-State Circuits Society, 2021, 1: 129-139.

KAESSER P, ISMAIL O, RUDORF C, et al . Linear-exponential I-DS ADCs: analysis, limitations and higher order[C ] //2023 IEEE International Symposium on Circuits and Systems (ISCAS). Monterey: IEEE, 2023. 1-5.

MOKHTAR M A, VOGELMANN P, ABDELAAL A, et al . FIR DACs in CT incremental delta-sigma modulators[C ] //2020 IEEE Inter national Symposium on Circuits and Systems (ISCAS). Seville: IEEE, 2020: 1-5.

PAVAN S, HALDER T, KANNAN A. continuous-time incremental delta-sigma modulators with FIR feedback[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 68(8): 3222-3231.

WANG B, SIN S W, SENG-PAN U, et al . A 1.2 V 86dB SNDR 500 kHz BW linear-exponential multi bit incremental ADC using positive feedback in 65 nm CMOS[C ] //2019 IEEE Asian Solid-State Circuits Conference (A-SSCC). Macau: IEEE, 2019: 117-120.

WANG B, SIN S W, U S P, et al . A 550-μW 20-kHz BW 100.8-dB SNDR linear-exponential multi bit incremental ΣΔ ADC with 256 clock cycles in 65-nm CMOS[J ] . IEEE Journal of Solid-State Circuits, 2019, 54(4): 1161-1172.

SUN A Y, WEN P X, SHAO H X, et al . A review of high-resolution audio sigma-delta modulator[J ] . Journal of Electronics Information Technology, 2024, 46(5): 1874-1887.

CHAE H, FLYNN M P. A 69 dB SNDR, 25 MHz BW, 800 MS/s continuous-time bandpass Δ-Σ modulator using a duty-cycle-controlled DAC for low power and reconfigurability[J]. IEEE Journal of Solid-State Circuits, 2016, 51(3): 649-659.

BILLA S, SUKUMARAN A, PAVAN S. Analysis and design of continuous-time delta-sigma converters incorporating chopping[J]. IEEE Journal of Solid-State Circuits, 2017, 52(9): 2350-2361.

JANG M, LEE C, CHAE Y. A 134-μW 99.4-dB SNDR audio continuous-time delta-sigma modulator with chopped negative-R and Tri-level FIR-DAC[J]. IEEE Journal of Solid-State Circuits, 2021, 56(6): 1761-1771.

MOKHTAR M A, ABDELAAL A, SPORER M, et al . A 0.9-V calibration-free 97 dB-SFDR 2-MS/s continuous time incremental delta-sigma ADC utilizing variable bit width quantizer in 28 nm CMOS[C ] //2021 IEEE Custom Integrated Circuits Conference (CICC). Austin: IEEE, 2021. 1-2.

YUAN M, JIAN M, ZHENG J, et al . Behavioral modeling and circuit design of high precision low power dynamic zoom ADC[J ] . Journal of Physics: Conference Series, 2023, 2477(1): 012074.

SOURI K, MAKINWA K A A. A 0.12 mm 2 7.4 μW micropower temperature sensor with an inaccuracy of ±0.2 ℃ (3σ) from −30 ℃ to 125 ℃[J ] . IEEE Journal of Solid-State Circuits, 2011, 46(7): 1693-1700.

GÖNEN B, SEBASTIANO F, QUAN R, et al . A dynamic zoom ADC with 109-dB DR for audio applications[J ] . IEEE J ournal of Solid-State Circuits, 2017, 52(6): 1542-1550.

CHOI Y, LEE W, PARK S, et al . A 101.6-dB-SNDR fully dynamic zoom adc using miller-compensated floating inverter amplifiers[J ] . IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(9): 4141-4145.

MA T, YUAN M, WANG Z, et al . A 180 µW dynamic zoom adc with 110 dB SNDR in 2 kHz BW[C ] //2023 IEEE MTT-S International Wireless Symposium (IWS). Qingdao: IEEE, 2023: 1-3.

ZHAO Y, ZHAO M, TAN Z. Fully dynamic zoom-adc based on improved swing-enhanced FIAs using CLS technique with 1250× bandwidth/power scalability[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(6): 1901-1905.

LIANG Y, REN J, CHEN L, et al . A reconfigurable 12-to-18 bit dynamic zoom ADC with pole-optimized technique[J ] . IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(5): 1940-1948.

KIM K S, KIM J, CHO S H. Nth-order multi bit ΣΔ ADC using SAR quantiser[J]. Electronics Letters, 2010, 46(19): 1315-1316.

SALGADO G M, O’HARE D, O’CONNELL I. Recent advances and trends in noise shaping SAR ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2020, 68(2): 545-549.

LI S, QIAO B, GANDARA M, et al . A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure[J ] . IEEE Journal of Solid-State Circuits, 2018, 53(12): 3484-3496.

JIE L, TANG X, LIU J, et al . An overview of noise-shaping SAR ADC: from fundamentals to the frontier[J ] . IEEE Open Journal of the Solid-State Circuits Society, 2021, 1: 149-161.

CHEN Z, MIYAHARA M, MATSUZAWA A. A 9.35-ENOB, 14.8 fJ/conv. -step fully-passive noise-shaping SAR ADC[C]//2015 Symposium on VLSI Circuits (VLSI Circuits). Kyoto: IEEE, 2015: C64-C65.

WANG T H, WU R, GUPTA V, et al . A 13.8-ENOB fully dynamic third-order noise-shaping SAR ADC in a single-amplifier EF-CIFF structure with hardware-reusing k T / C noise cancellation[J ] . IEEE Journal of Solid-State Circuits, 2021, 56(12): 3668-3680.

ZHANG H, WANG X, LI N, et al . A 2.5-mhz bw, 75-dB SNDR noise-shaping SAR ADC with a 1st-order hybrid EF-CIFF structure assisted by unity-gain buffer[J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, 30(12): 1928-1932.

JIE L, ZHENG B, CHEN H W, et al . A cascaded noise-shaping SAR architecture for robust order extension[J ] . IEEE Journal of Solid-State Circuits, 2020, 55(12): 3236-3247.

LIU J, LI D, ZHONG Y, TANG X, et al . A 250 kHz-BW 93 dB-SNDR 4th-order noise-shaping SAR using capacitor stacking and dynamic buffering[C ] //2021 IEEE International Solid-State Circuits Conference (ISSCC). San Francisco: IEEE, 2021. 369-371.

BAIRD R T, FIEZ T S. Linearity enhancement of multibit Δ-Σ A/D and D/A converters using data weighted averaging[J]. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995, 42(12): 753-762.

OBATA K, MATSUKAWA K, MIKI T, et al . A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect[C ] //2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits). Honolulu: IEEE, 2016. 1-2.

SHU Y S, KUO L T, LO T Y. An oversampling SAR ADC with DAC mismatch error shaping achieving 105 dB SFDR and 101 dB SNDR over 1 kHz BW in 55 nm CMOS[J]. IEEE Journal of Solid-State Circuits, 2016, 51(12): 2928-2940.

JIAN M, ZHENG J, KONG X, et al . A 73-dB-SNDR 2nd-Order noise-shaping SAR with a low-noise time-domain comparator[J ] . IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, 71(8): 3645-3649.

LI H, SHEN Y, CANTATORE E, et al . A 77.3-dB SNDR 62.5-kHz bandwidth continuous-time noise-shaping SAR ADC with duty-cycled Gm-C integrator[J ] . IEEE Journal of Solid-State Circuits, 2023, 58(4): 939-948.

OH S, OH Y, LEE J, et al . An 85 dB DR 4 MHz BW pipelined noise-shaping SAR ADC with 1-2 MASH structure[J ] . IEEE Journal of Solid-State Circuits, 2021, 56(11): 3424-3433.

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