基于增益增强型全差分环形放大器的16位流水线逐次逼近型模数转换器

郑基炜; 郭春炳

doi:10.12052/gdutxb.240029

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基于增益增强型全差分环形放大器的16位流水线逐次逼近型模数转换器

集成电路科学与工程 | 更新时间：2026-05-27

- 基于增益增强型全差分环形放大器的16位流水线逐次逼近型模数转换器
- A 16-bit Pipelined-SAR ADC with a Gain-enhanced Fully Differential Ring Amplifier
- 广东工业大学学报 2024年41卷第6期页码：20-25
- 作者机构：
  
  1. 广东工业大学信息工程学院,广东,广州,510006
  2. 广东工业大学集成电路学院,广东,广州,510006
- 作者简介：
  
  郑基炜(1999–)，男，硕士研究生，主要研究方向为高精度模数转换器，E-mail：767621321@qq.com
  郭春炳(1971–)，男，教授，博士，主要研究方向为模数混合集成电路设计，E-mail：cbguo@gdut.edu.cn
- 基金信息：
  
  广东省重点领域研发计划项目(2018B010115002)
- DOI：10.12052/gdutxb.240029
  中图分类号： TN453
- 纸质出版：2024
- 稿件说明：
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郑基炜, 郭春炳. 基于增益增强型全差分环形放大器的16位流水线逐次逼近型模数转换器[J]. 广东工业大学学报, 2024, 41(6): 20-25.

Zheng Ji-wei, Guo Chun-bing. A 16-bit Pipelined-SAR ADC with a Gain-enhanced Fully Differential Ring Amplifier[J]. 2024, 41(6): 20-25.
郑基炜, 郭春炳. 基于增益增强型全差分环形放大器的16位流水线逐次逼近型模数转换器[J]. 广东工业大学学报, 2024, 41(6): 20-25. DOI： 10.12052/gdutxb.240029.

Zheng Ji-wei, Guo Chun-bing. A 16-bit Pipelined-SAR ADC with a Gain-enhanced Fully Differential Ring Amplifier[J]. 2024, 41(6): 20-25. DOI： 10.12052/gdutxb.240029.

摘要

在高精度流水线逐次逼近型模数转换器(pipelined-SAR ADC)中，需要使用高开环增益的运算放大器来提高闭环级间残差放大器的增益精度。本文提出的环形放大器使用增益增强型输出级提高开环增益和稳定性，可以实现超过90 dB的开环增益，在不采用任何校准技术的情况下可以显著减小级间残差增益误差，满足16位ADC的精度要求。该ADC基于65 nm CMOS工艺设计，芯片面积为0.256 mm

。在25 MS/s的采样速率以及接近奈奎斯特频率输入信号的条件下，所设计的ADC仿真测得的信噪失真比(Signal-to-noise Distortion Ratio

SNDR)和无杂散动态范围(Spurious Free Dynamic Range

SFDR)分别为77.8 dB和96.8 dB，功耗为2.8 mW，品质因数FoMw和FoMs分别为18.0 fJ/ con.-step和174.3 dB。

Abstract

In pipelined-successive approximation register analog-to-digital converter (pipelined-SAR ADC)

it is necessary to use large-open-loop gain operational amplifiers to improve the gain accuracy of closed-loop residual amplifications. The proposed ring amplifier uses a gain-enhanced output stage to improve the open-loop gain and stability

achieving an open-loop gain of over 90 dB and significantly reducing the residue gain errors without any calibration techniques

meeting the accuracy requirement of a 16 bit ADC. The ADC is implemented in the 65 nm CMOS process with an active area of 0.25

6 mm

. At a sampling rate of 25 MS/s and with Nyquist-rate input

the proposed ADC achieves simulated signal-to-noise distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 77.8 dB and 96.8 dB

respectively

with a power consumption of 2.8 mW. The proposed ADC achieves Walden and Schreier figure-of-merit (FoM) of 18.0 fJ/conversion-step and 174.3 dB

respectively.

关键词

Keywords

references

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