3D NAND闪存P/E次数的快速测评与寿命预测

罗铮; 韩国军

doi:10.12052/gdutxb.240023

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3D NAND闪存P/E次数的快速测评与寿命预测

集成电路科学与工程 | 更新时间：2026-05-27

- 3D NAND闪存P/E次数的快速测评与寿命预测
- Rapid Measurement and Lifetime Prediction of 3D NAND Flash P/E Cycles
- 广东工业大学学报 2024年41卷第6期页码：52-59
- 作者机构：
  
  广东工业大学信息工程学院,广东,广州,510006
- 作者简介：
  
  罗铮(1999–) ，男，硕士研究生，主要研究方向为3D NAND闪存错误特性，E-mail：1145806026@qq.com
  韩国军(1974–) ，男，教授，主要研究方向为信息论与差错控制编译码技术、存储器件与系统、智能通信与车联网等，E-mail：gjhan@gdut.edu.cn
- 基金信息：
  
  NSFC-广东省联合基金项目(U2001203)
- DOI：10.12052/gdutxb.240023
  中图分类号： TP333
- 纸质出版：2024
- 稿件说明：
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罗铮, 韩国军. 3D NAND闪存P/E次数的快速测评与寿命预测[J]. 广东工业大学学报, 2024, 41(6): 52-59.

Luo Zheng, Han Guo-jun. Rapid Measurement and Lifetime Prediction of 3D NAND Flash P/E Cycles[J]. 2024, 41(6): 52-59.
罗铮, 韩国军. 3D NAND闪存P/E次数的快速测评与寿命预测[J]. 广东工业大学学报, 2024, 41(6): 52-59. DOI： 10.12052/gdutxb.240023.

Luo Zheng, Han Guo-jun. Rapid Measurement and Lifetime Prediction of 3D NAND Flash P/E Cycles[J]. 2024, 41(6): 52-59. DOI： 10.12052/gdutxb.240023.

摘要

基于3D三层单元NAND闪存的固态硬盘由于存储密度高、每比特成本低，正逐渐成为大规模存储系统中占主导地位的存储介质。随着技术的发展，3D NAND闪存芯片的存储密度越来越高，可靠性也越来越差。可靠性的降低和厂商制定寿命标称值过于保守导致闪存芯片在未达到实际寿命前被过早地淘汰，造成不必要的浪费。通过机器学习预测模型对闪存芯片进行寿命预测可以优化存储策略，有效延长寿命并减少损失。然而因生产工艺差异，导致闪存芯片之间的错误特性有一定的不同，会影响对闪存芯片寿命预测的准确度。本文经过实验发现数据保留错误的误比特率可用来表征擦/写次数，并提出通过将相邻字线写入特定内容的方法激励字线间干扰，可有效减少耗时并提高寿命预测准确率，经验证可缩短耗时约90.9%，预测准确率可提高33.3个百分点。

Abstract

Solid State Disks based on 3D triple cell NAND flash has becoming a dominant storage medium in mass storage systems due to their high storage density and low cost per bit. With the rapid development of technologies

3D NAND flash chips are becoming less reliable with high storage densities. Reduced reliability and overly conservative manufacturers' formulation of lifetime nominal values result in flash chips being prematurely phased out before reaching their actual lifespan with unnecessary waste. Lifetime prediction of flash chips through machine learning-based prediction models can optimize storage strategies to effectively extend lifetime and reduce losses. However

due to the differences in production processes

the error characteristics of flash memory chips are somewhat different from each other

which affects the accuracy of the life prediction of flash memory chips. In this paper

we experimentally find that the bit error rate of data retention errors can be used to characterize the number of program/erase cycles times

and propose to stimulate the interference between word-lines by writing specific contents to adjacent word-lines

which can effectively reduce the elapsed time and improve the accuracy of the life time prediction. Experimental results show that the elapsed time can be shorten by about 90.9%

and the prediction accuracy can be improved by 33.3 percentage points.

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references

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