基于单调排序与并行选择的连续删除堆栈译码器的硬件实现

曾文坦; 叶龙建; 翟雄飞; 韩国军

doi:10.12052/gdutxb.220180

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基于单调排序与并行选择的连续删除堆栈译码器的硬件实现

综合研究 | 更新时间：2026-05-27

- 基于单调排序与并行选择的连续删除堆栈译码器的硬件实现
- The Implementation of Successive Cancellation Stack Decoder Based on Monotone Sorting and Parallel Comparison
- 广东工业大学学报 2024年41卷第1期页码：101-109
- 作者机构：
  
  广东工业大学信息工程学院,广东,广州,510006
- 作者简介：
  
  曾文坦(1997–) ，男，硕士研究生，主要研究方向为信道编译码FPGA设计实现
  翟雄飞(1990–) ，男，讲师，博士，主要研究方向为FPGA和信号处理技术，E-mail: zhaixiongfei@gdut.edu.cn
- 基金信息：
  
  NSFC-广东省联合基金资助项目(U2001203);广东省重点领域研发计划项目(2021B1101270001);广州市基础与应用基础研究项目(202102020869);广东省自然科学基金资助面上项目(2022A1515010153)
- DOI：10.12052/gdutxb.220180
  中图分类号： TN929.5
- 网络首发：2024-01-25，
  
  纸质出版：2024
- 稿件说明：
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曾文坦, 叶龙建, 翟雄飞, 韩国军. 基于单调排序与并行选择的连续删除堆栈译码器的硬件实现[J]. 广东工业大学学报, 2024, 41(1): 101-109.

Zeng Wen-tan, Ye Long-jian, Zhai Xiong-fei, et al. The Implementation of Successive Cancellation Stack Decoder Based on Monotone Sorting and Parallel Comparison[J]. 2024, 41(1): 101-109.
曾文坦, 叶龙建, 翟雄飞, 韩国军. 基于单调排序与并行选择的连续删除堆栈译码器的硬件实现[J]. 广东工业大学学报, 2024, 41(1): 101-109. DOI： 10.12052/gdutxb.220180.

Zeng Wen-tan, Ye Long-jian, Zhai Xiong-fei, et al. The Implementation of Successive Cancellation Stack Decoder Based on Monotone Sorting and Parallel Comparison[J]. 2024, 41(1): 101-109. DOI： 10.12052/gdutxb.220180.

摘要

极化码得益于其较低的复杂度和灵活的构造，成为了当今最为流行的信道编码方式。然而，与其他信道编码的译码算法相比，极化码中的连续删除 (Successive Cancellation

SC) 译码算法的性能较差。为了解决这一问题，连续删除列表(Successive Cancellation List

SCL) 、连续删除堆栈(Successive Cancellation Stack

SCS) 等基于连续删除译码的改进算法问世，并显著地改善了其纠错性能。其中，连续删除堆栈译码算法是以更高的复杂度为代价的，特别是在路径选择过程中。本文提出了一种新型的路径选择硬件架构，该架构通过对路径信息分组存储，用分组单调排序与并行比较相结合的策略进行最优路径选择，降低了硬件资源消耗的同时提高了路径选择的硬件效率。最后在现场可编程门阵列(Field Programmable Gate Array

FPGA) 上实现了该架构，硬件实现结果验证了本文提出的架构与现有的SCS译码器拥有相近的纠错性能的同时，整体资源开销在查找表(Look Up Table

LUT)、寄存器(Register)和块随机存储器(Block Random Access Memory

BRAM)上分别减少了24.06%，56.42%和39.29%，吞吐率提高了24.38%。

Abstract

Due to the low complexity and flexible construction

polar code has become one of the most popular channel codings in wireless communication. However

the conventional successive cancellation (SC) decoder suffers from the modest performance. To deal with this issue

some improved decoders

such as successive cancellation stack (SCS) and successive cancellation list (SCL)

are developed with significant improvement of bit error ratio. However

the performance improvement of these methods is at the cost of high complexity

especially in the procedure of path selection. In this work

we propose a new hardware architecture of path selection by combining the monotone sorting of groups with the parallel comparison

which enhances the performances of hardware efficiency and resource utilization. By exploiting our proposed architecture

the results of the implementation on field programmable gate array (FPGA) verify that the hardware consumptions of the look up table (LUT)

56.42% and 39.29% respectively. And the throughput is improved by 24.38% as compared with the existing architectures.

关键词

Keywords

references

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