Abstract: Due to the inherent parasitic inductances in power devices caused by chip packaging and circuit design, issues such as gate signal oscillations and increased electrical stresses frequently occur. While complete elimination of parasitic inductance remains impractical, effective utilization of the energy stored in these inductances offers a more viable approach to controlling power device switching transients. This paper presents a comprehensive parasitic inductance model for power devices and packaging using a distributed parameter coupling extraction method. The energy interactions within parasitic inductors are analyzed through an instantaneous energy integration approach. Novel energy transfer branches are proposed to facilitate both energy transfer across parasitic inductors and the shunting of displacement currents induced by dv_ce/dt enabling independent control of voltage and current slopes. This technique achieves simultaneous optimization of switching losses and electrical stresses without requiring high-cost components. Experimental validation is conducted using IGBT device IKW75N60T in a double-pulse test setup, demonstrating significant performance improvements: 12.0% reduction in current overshoot, 14.5% reduction in voltage overshoot, along with 4.16% and 7.6% reductions in turn-on and turn-off losses respectively. The proposed method provides an effective solution for managing switching transients while maintaining cost efficiency in power electronic systems.