屠腾, 张方华, 张钊荣, 黄恩泽, 余文浩. 基于矩阵磁结构的平面电感寄生电容优化设计[J]. 中国电机工程学报, 2024, 44(7): 2825-2832. DOI: 10.13334/j.0258-8013.pcsee.221702
引用本文: 屠腾, 张方华, 张钊荣, 黄恩泽, 余文浩. 基于矩阵磁结构的平面电感寄生电容优化设计[J]. 中国电机工程学报, 2024, 44(7): 2825-2832. DOI: 10.13334/j.0258-8013.pcsee.221702
TU Teng, ZHANG Fanghua, ZHANG Zhaorong, HUANG Enze, YU Wenhao. Optimal Design of Parasitic Capacitance Based on Matrix Magnetics for Planar Inductor[J]. Proceedings of the CSEE, 2024, 44(7): 2825-2832. DOI: 10.13334/j.0258-8013.pcsee.221702
Citation: TU Teng, ZHANG Fanghua, ZHANG Zhaorong, HUANG Enze, YU Wenhao. Optimal Design of Parasitic Capacitance Based on Matrix Magnetics for Planar Inductor[J]. Proceedings of the CSEE, 2024, 44(7): 2825-2832. DOI: 10.13334/j.0258-8013.pcsee.221702

基于矩阵磁结构的平面电感寄生电容优化设计

Optimal Design of Parasitic Capacitance Based on Matrix Magnetics for Planar Inductor

  • 摘要: 当平面电感的单层绕组匝数超过一匝时,外侧绕组间存储的电场能量会导致寄生电容偏大。为降低平面电感寄生电容,文中将一个电感拆分为多个分立电感以实现单层一匝的绕制方案,并分析分立电感方案与单磁心方案在铁损、铜损和体积方面的变化。针对分立电感体积增大这一问题,进一步提出矩阵磁方案,给出两电感、四电感磁集成结构。有限元仿真结果表明,相接近的体积下,矩阵磁方案降低了77%的寄生电容,并减小了69%的铜损。最后,搭建一台Buck变换器。功率实验结果表明,矩阵磁结构平面电感具有更优的性能。

     

    Abstract: When the turns of the single-layer winding of the planar inductor exceeds one, the electric field energy stored between the outer windings will make the parasitic capacitance larger. To reduce the parasitic capacitance of the planar inductor, spliting an inductor into multiple discrete inductors to achieve a single-layer-one-turn winding scheme is proposed and the changes in core loss, copper loss and volume are analyzed. Aiming at reducing the volume of discrete inductors, a matrix magnetic scheme is proposed; two-inductor and four-inductor magnetic integrated structures are provided. The finite element simulation results show that the matrix magnetic scheme reduces the parasitic capacitance by 77%, and reduces the copper loss by 70%. Finally, a buck converter is built in this paper and the power experiment results show the planar inductance of the matrix magnetic structure has better performance.

     

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