Abstract: The arm reactor (AR) and current limiting reactor (CLR) of the high-voltage DC grid based on modular multilevel converters (MMC-HVDC) can effectively reduce the breaking current of the DC circuit breaker and realize the DC short-circuit fault ride-through while ensuring the steady-state performance of the system with the reasonable coordination of the current limiter (fault current limiter, FCL). In this paper, firstly, the temporal and spatial distributions of transient energy flow (TEF) of the system energy storage components and the AC/DC regions in the MMC-HVDC grid and its relevance to the evolution of the DC short-circuit fault current under DC short-circuit fault conditions were analyzed. Secondly, a comprehensive parameter optimization model based on TEF suppression was proposed, in which TEF suppression rate and suppression efficiency to be maximized for the AC areas, sub-module capacitances and adjacent DC lines were considered as objectives, and AR, CLR, FCL parameters as optimization variables. Finally, taking the topology of Zhangbei four-terminal DC power network with pole-to-ground faults as an example, the values of AR, CLR and FCL were optimized by the proposed model. The optimization results and analysis show that by the proposed model the respective capabilities of AR, CLR and FCL in suppressing short-circuit fault currents can be fully utilized while taking into account of both technical and economic performances in fault current suppression, which reduces the cost of current limiting.