Abstract: SiC MOSFET power electronic device is very likely to be driven into avalanche mode with the coupling of high di/dt and parasitic inductance. In view of existing ordinary experimental analysis, which is difficult to reveal the problem that different avalanche shock mode could lead to different failure mechanism, the failure mechanism of SiC MOSFET under single and repetitive avalanche shocks was investigated. Firstly, unclamped inductive switching（UIS） experimental bench for avalanche test was constructed, as well as the simulation model in cell level. Secondly, on the basis of single pulse avalanche shock experiment, corresponding failure model was built, and the distribution of thermal-electrical property during the process of failure evolution was analyzed by simulation model with single shock. Finally, the failure evolutionary model was constructed based on experiment of repetitive avalanche shock, and corresponding degradation parameter was studied with the help of repetitive avalanche failure model, which is used to investigate the distribution regularity of electric field in SiC MOSFET cell under repetitive avalanche shock. The experimental and simulation results show that parasitic BJT lunch-up leads to the failure of single pulse avalanche shocks. While, the increase of fixed charge in oxide by trapping holes contributes to decrease of threshold voltage of SiC MOSFET and its repetitive avalanche failure.