Abstract: The space vector modulation (SVPWM) strategy has the advantages of high DC voltage utilization and good control flexibility, which is widely used in the field of power electronics. However, the strategy needs to avoid the influence of narrow pulse for safe operation of the devices. In this paper, the principle of three-level space vector modulation is given, and the generation mechanism of narrow pulse under space vector modulation is analyzed. Secondly, the accurate proportion of narrow pulse in the output voltage is deduced analytically, and the influence of narrow pulse on the harmonic performance of output voltage is summarized. On the basis of the above, a narrow pulse suppression strategy based on vector time length adjustment is proposed, which realizes the seven-section symmetric modulation with both narrow pulse suppression and capacitor voltage balance, and reduces the influence of narrow pulse restriction on the output voltage harmonics. Finally, based on the offline simulation model and the hardware in loop real-time simulation platform, the correctness and effectiveness of the narrow pulse suppression strategy proposed in this paper are verified.