Implementation of DMA Controller on Navigation Baseband SoC

Zhang Ye-qiang; Liu Yi-jun

doi:10.3969/j.issn.10077162.2016.01.007

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Implementation of DMA Controller on Navigation Baseband SoC

更新时间：2026-05-27

- Implementation of DMA Controller on Navigation Baseband SoC
- Vol. 33, Issue 1, Pages: 36-39(2016)
- 作者机构：
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- DOI：10.3969/j.issn.10077162.2016.01.007
  CLC：
- Online First：16 January 2016，
  
  Published：2016
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张业强, 刘怡俊. DMA控制器在导航基带SoC中的应用[J]. 广东工业大学学报, 2016, 33(1): 36-39.

Zhang Ye-qiang, Liu Yi-jun. Implementation of DMA Controller on Navigation Baseband SoC[J]. 2016, 33(1): 36-39.
张业强, 刘怡俊. DMA控制器在导航基带SoC中的应用[J]. 广东工业大学学报, 2016, 33(1): 36-39. DOI： 10.3969/j.issn.10077162.2016.01.007.

Zhang Ye-qiang, Liu Yi-jun. Implementation of DMA Controller on Navigation Baseband SoC[J]. 2016, 33(1): 36-39. DOI： 10.3969/j.issn.10077162.2016.01.007.

摘要

讨论了DMA控制器在基于RTEMS的高性能GPS接收机中的架构设计，实现DMA IP与导航基带整体系统的良好融合.设计了DMA IP的硬件结构，利用复用的思想充分发挥硬件性能，使用寄存器结构和FIFO缓存结构实现了读写控制，并用Verilog HDL语言设计实现了DMA控制器，最后在Altera Cyclone4 FPGA上完成了设计验证.结果表明，DMA控制器能减轻导航基带SoC芯片的处理器负担，缩短捕获跟踪时间，提高系统整体性能.

Abstract

This article discusses the architecture design of DMA controller on high performance GPS receiver based on RTEMS which achieves the optimal integration of DMA IP and navigation baseband system. The authors designed the hardware architecture of DMA IP and made full use of hardware performance with the idea of multiplexing

then used register and FIFO buffer to achieve read-write control. Furthermore

the researchers designed the DMA controller with Verilog HDL and verified the design on Altera Cyclone4 FPGA. The result demonstrates that DMA controller can ease the CPU’s burden and shorten the acquisition & tracking time which improves the performance of the whole system.

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