Yumeng Cai, Tong Sun, Peng Sun, et al. Influence of Parasitic Parameters on Dynamic Threshold Voltage Hysteresis of Silicon Carbide MOSFETs[J]. CSEE Journal of Power and Energy Systems, 2023, 9(6): 2251-2262.
DOI:
Yumeng Cai, Tong Sun, Peng Sun, et al. Influence of Parasitic Parameters on Dynamic Threshold Voltage Hysteresis of Silicon Carbide MOSFETs[J]. CSEE Journal of Power and Energy Systems, 2023, 9(6): 2251-2262.DOI: 10.17775/CSEEJPES.2022.00480.
Influence of Parasitic Parameters on Dynamic Threshold Voltage Hysteresis of Silicon Carbide MOSFETs
Threshold voltage (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{TH}}$) hysteresis affects the dynamic characteristics of silicon carbide (SiC) MOSFETs
which in turn affects reliability of a device. In this paper
a dynamic hysteresis curve is proposed as an evaluation method of the influence of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{TH}}$ hysteresis on the switching characteristics of SiC MOSFETs. This method can eliminate the impact of trigger level and obtain the dynamic <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{TH}}$. Furthermore
the influence of parasitic parameters on dynamic <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{TH}}$ hysteresis is theoretically analyzed. Double pulse tests under different parasitic parameters are performed on three SiC MOSFETs with different gate structures to verify the analysis. Results show that gate resistance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\mathrm{G}}$) and source inductance (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{\mathrm{S}}$) have more significant effects on dynamic <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{TH}}$ hysteresis compared with gate inductance and drain inductance. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{TH}}$ hysteresis phenomenon weakens with increase of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{\mathrm{G}}$ or <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L_{\mathrm{S}}$
which is related to device structure. The results presented in this paper can provide guidance for the design of circuit parasitic parameters of SiC MOSFETs to regulate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{TH}}$ hysteresis.