Economical and reliable protection of DC-side short-circuit faults has become a key technology for promoting the development of module multilevel converters based on the high voltage direct current grid (MMC-HVDC-Grid). The fault current limiter (FCL) can effectively suppress the rapid development of the fault current and reduce the current breaking capacity of the circuit breaker. In this paper

a method based on transient energy flow (TEF) analysis is proposed to optimize the allocation of a resistive and inductive FCL in the MMC-HVDC-Grid. In the proposed method

the electromagnetic TEF is measured first

and then

the TEF suppression rate and suppression efficiency are defined as optimization objectives

and the installation location of the FCL and its impedance parameters as optimization variables. To test the proposed method

two-terminal and four-terminal bipolar MMC-HVDC-Grids with single-pole-to-ground DC faults are modeled in the PSCAD/EMTDC so that the TEF data can be acquired. The optimal FCLs' location and parameter values are determined through investigating the evolution paradigm of TEF along with changes of the FCL position and parameters. The results prove that the selected parameters can effectively slow down the DC fault current rising rate

thus reducing the requirements on tripping current of the DC breakers.