Silicon carbide (SiC) MOSFETs

with their superior performance

have broad application prospects in high-voltage power conversion fields. However

when employed in parallel configurations under high current conditions

differences in circuit parameters and chip characteristics may result in current imbalance among the parallel chips. This imbalance leads to junction temperature variations

which may cause reliability issues and

in severe cases

lead to failure of the parallel chips. To mitigate the current imbalance among parallel chips

this paper first analyzes the dynamic current distribution characteristics of parallel chips under asymmetric layouts and establishes the correlation between current distribution and threshold voltage. Subsequently

a dynamic current balancing chip sorting method for paralleled SiC MOSFETs is proposed. This method utilizes the dispersion in chip threshold voltages to group the chips

thereby compensating for the asymmetry in circuit parameters and reducing dynamic current imbalance. Finally

experimental validation is conducted

and the results demonstrate that the proposed sorting method can be adopted to significantly improve the current balancing performance of paralleled SiC MOSFETs.