The high parasitic inductance inherent in traditional packaging significantly limits the switching speed of series-connected SiC MOSFETs. This paper presented a π-shaped ultra-compact packaging solution designed for chip-level high-voltage series SiC MOSFET module

reducing the 16-stage/20 kV serial switch's parasitic inductance to 55.8 nH. The impact of structural parameters in the ultra-compact packaging on the parasitic inductance and electric field distribution was investigated. The results demonstrate that reducing board spacing substantially lowers the parasitic inductance

and this reduction encounters limitations imposed by insulation. To overcome the insulation challenges associated with ultra-compact packaging while realizing extreme parasitic inductance reduction

two corresponding methods were proposed as follows: a partial discharge detection method based on common-mode charge measurement for accurate partial discharge inception voltage (PDIV) detection under pulsed electric stress

and an insulation enhancement strategy employing hexagonal boron nitride filler modification combined with composite silicone rubber. PDIV confirms that the modified material satisfies the insulation requirements of reducing board spacing configurations

thereby enabling ultimate parasitic inductance minimization. Furthermore

to facilitate the application of this module in pulsed power

a hybrid drive scheme combining unitized magnetic isolation and capacitive self-triggering was developed. This approach ensures drive isolation and withstand voltage while enhancing multi-stage MOSFET synchronization and switching speed

achieving 16-stage SiC MOSFET module simultaneous turn-on within 26 ns. Compared to the TO-247 packaged module

the proposed ultra-compact packaging-based pulse power module demonstrates significantly improved switching speed. Moreover

operational measurements confirm adequate thermal management capability during module operation.