LU Zhan, 1, LI Kemeng, et al. Accelerating Static Security Analysis Using Nested Dissection and Load Balancing Parallelism[J]. 2026, 50(3): 946-954.
DOI:
LU Zhan, 1, LI Kemeng, et al. Accelerating Static Security Analysis Using Nested Dissection and Load Balancing Parallelism[J]. 2026, 50(3): 946-954. DOI: 10.13335/j.1000-3673.pst.2025.1313.
Accelerating Static Security Analysis Using Nested Dissection and Load Balancing Parallelism
With the increasing uncertainties on both source and load sides in modern power systems
there is an urgent need to enhance the computational efficiency of static security analysis (SSA) to meet the demand from dispatch centers for higher-frequency grid state awareness. To this end
this paper explores the potential of graph computing in this domain and proposes an integrated acceleration workflow based on our self-developed graph computing system. The core of this workflow is twofold. Firstly
an efficient nested dissection node ordering strategy is implemented by leveraging the built-in graph coarsening and multilevel partitioning capabilities of the graph computing framework. This strategy employs graph partitioning and parallel techniques to accelerate reordering of grid node indices
thereby reducing fill-ins during subsequent factorization and improving the efficiency of individual power flow calculations. Secondly
to fully leverage multi-core resources and overcome load imbalance in parallel computing
a load-balancing multi-threaded parallel method is designed and implemented. By combining a global task queue with thread-local task queues
this method effectively reduces thread synchronization overhead and improves parallel acceleration performance. Finally
the integrated method
combining the graph-based node ordering and parallel techniques
was tested on large-scale power grids (e.g.
3012-node and 13659-node systems). The results validate that the proposed method holds a significant advantage over existing static security analysis algorithms based on conventional nested dissection ordering and OpenMP-based parallelism.