Multisampling technology can simultaneously reduce 1.5 beats of digital control delay to improve bandwidth. However

when designing the control loop based on the average model of multisampling pulse width modulation (PWM)

the bandwidth may even exceed switching frequency fsw

which is obviously unreasonable. So

it is not clear how to design or analyze loop bandwidth of voltage source converters (VSCs) under multisampling. By taking the classic single-phase VSC as an example

from the perspective of modulation physical characteristics

this article derives and analyzes the physical upper limit of loop bandwidth under multisampling

which is about fsw/3

based on two conditions: the slope of signals within bandwidth is bounded by that of the triangular carrier and the modulation sidebands remain non-overlapping with the in-band signal components. Then

the current loop bandwidth under multi sampling is analyzed from three aspects: sampling rate N

ripple suppression method

and accurate model of multisampling PWM. A ripple suppression method based on cascaded band stop filter (BSF) is proposed

which has almost no phase lag within fsw/3 andis beneficial for improving bandwidth. In response to the inaccuracy of the traditional multisampling average model

based on the multi-sampling PWM multifrequency model

the accurate open-and closed-loop transfer functions of L-and LCL-type VSCs are derived

and the stability and bandwidth analysis results would be more accurate. The above analysis can provide reference for loop bandwidth design of multi-sampled VSC

so as to clarify the bandwidth limiting factors and theoretical upper limits. Finally

the experimental results validated the correctness of the theoretical analysis mentioned above.