Modeling of 3D NAND Memory Cells with Taper Angle and Programming Strategy Optimization

Lin Xuntao; Han Guojun

doi:10.12052/gdutxb.250167

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Modeling of 3D NAND Memory Cells with Taper Angle and Programming Strategy Optimization

更新时间：2026-05-27

- Modeling of 3D NAND Memory Cells with Taper Angle and Programming Strategy Optimization
- Vol. 43, Issue 2, Pages: 91-100(2026)
- 作者机构：
  
  广东工业大学信息工程学院,广东,广州,510006
- 作者简介：
- 基金信息：
- DOI：10.12052/gdutxb.250167
  CLC： TP333
- Published：2026
- 稿件说明：
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林训涛, 韩国军. 融合沟道倾斜角的3D NAND存储单元建模及编程策略优化[J]. 广东工业大学学报, 2026, 43(2): 91-100.
林训涛, 韩国军. 融合沟道倾斜角的3D NAND存储单元建模及编程策略优化[J]. 广东工业大学学报, 2026, 43(2): 91-100. DOI： 10.12052/gdutxb.250167.

DOI： 10.12052/gdutxb.250167

摘要

随着3D NAND闪存堆叠层数的不断增加，深孔刻蚀工艺造成的深宽比也相应增加，由此形成的沟道倾斜角导致存储单元阈值电压分布展宽，影响了器件存储可靠性。当前针对该问题的解决方案主要包括刻蚀优化、沟道补偿等工艺方法，以及纠错编码、读重试等策略，然而这些方法普遍面临实现复杂、硬件开销大等问题。为克服上述局限性并有效地降低倾斜角的影响，本文首先基于 Sentaurus TCAD 平台构建了含倾斜角的存储串仿真模型，验证分析了深孔倾角对阈值电压分布梯度的影响，在此基础上，提出了一种相邻单元导通电压幅度动态调整的策略，该策略根据目标存储单元在存储串中的垂直位置，差异化调整其相邻字线的导通电压值，以精准补偿因沟道倾斜引起的纵向电压梯度。仿真结果表明，本文所提出的编程策略与传统编程策略相比，在线性调节模式下，最大电压差与分布标准差分别降低了62.4%与61.4%；在非线性调节模式下，二者分别降低了 63.7%与 64.3%，同时将相邻单元的阈值电压扰动控制在 3 mV以内，且在不同编程时间下写入速率保持稳定。

Abstract

With the continuous increase in the number of stacking layers in 3D NAND flash memory

the aspect ratio caused by deep hole etching processes also increases accordingly. The resulting taper angle leads to a broadening of the threshold voltage distribution of memory cells

adversely affecting device storage reliability. Current solutions to this problem primarily include process-based methods such as etching optimization and channel compensation

or strategies like error correction coding and read-retry. However

these approaches generally face challenges such as implementation complexity and high hardware overhead. To overcome these limitations and effectively mitigate the impact of the taper angle

a simulation model of a memory string incorporating taper angles is first constructed based on the Sentaurus TCAD platform

validating and analyzing the influence of deep hole taper on the threshold voltage distribution gradient. On this basis

a strategy for dynamic optimization of the pass voltage amplitude in adjacent cells is proposed. This strategy differentially optimizes the pass voltage of word lines adjacent to the target memory cell according to its vertical position in the memory string

thereby accurately compensating for the longitudinal voltage gradient induced by channel taper. Simulation results demonstrate that compared to conventional programming strategy

the proposed strategy optimizes the maximum voltage difference and the standard deviation of distribution

achieving reductions of 62.4% and 61.4%

respectively

in linear mode

and 63.7% and 64.3% in nonlinear mode

while constraining the threshold voltage disturbance of adjacent cells within 3 mV and maintaining stable programming speed.

关键词

Keywords

references

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