A Research on Logic Synthesis for Dual-domain Memristive Circuits

Yao Lian; Wu Jigang; Liu Peng

doi:10.12052/gdutxb.250162

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A Research on Logic Synthesis for Dual-domain Memristive Circuits

更新时间：2026-05-27

- A Research on Logic Synthesis for Dual-domain Memristive Circuits
- Vol. 42, Issue 6, Pages: 27-33(2025)
- 作者机构：
  
  广东工业大学计算机学院,广东,广州,510006
- 作者简介：
- 基金信息：
- DOI：10.12052/gdutxb.250162
  CLC： TP29
- Published：2025
- 稿件说明：
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姚廉, 武继刚, 刘鹏. 面向双逻辑域的忆阻逻辑综合研究[J]. 广东工业大学学报, 2025, 42(6): 27–33.

Yao Lian, Wu Jigang, Liu Peng. A Research on Logic Synthesis for Dual-domain Memristive Circuits[J]. 2025, 42(6): 27-33.
姚廉, 武继刚, 刘鹏. 面向双逻辑域的忆阻逻辑综合研究[J]. 广东工业大学学报, 2025, 42(6): 27–33. DOI： 10.12052/gdutxb.250162

Yao Lian, Wu Jigang, Liu Peng. A Research on Logic Synthesis for Dual-domain Memristive Circuits[J]. 2025, 42(6): 27-33. DOI： 10.12052/gdutxb.250162.

摘要

忆阻器不仅能够用于数据存储，还可以构建多种逻辑电路实现存内计算，有望成为打破“存储墙”瓶颈的核心基础器件。然而在大规模复杂电路设计场景中，现有的单逻辑域忆阻逻辑综合方案缺乏灵活性，综合后生成的电路各项性能难以满足设计需求。本文提出一种面向忆阻器蕴含逻辑和忆阻器非−蕴含逻辑的双逻辑域综合优化方法，通过分析2种逻辑在对电路网表进行映射和调度时的规律特性，在技术独立优化阶段(Technology Independent Optimization) 引入最小子结构重写、MUX析取/合取双态优选及多扇出集群节点协同优化策略，实现高性能图拓扑变换与调度。与ABC tool相比，本文所提出方法在映射后的节点数量上降低17.32%。与最新研究里的AND-OR方法相比，在调度时的面积开销方面降低61.5%。

Abstract

Memristors

originally exploited for nonvolatile storage

are now intensively investigated as logic primitives capable of in-memory computing

offering a promising solution to break the “memory wall”. However

when targeting the design of large and complex circuits

existing synthesis flows restricted to a single memristive logic lack the flexibility

leading to results that the performance metrics of circuits fall short of design targets. In this work

a dual-domain synthesis framework is proposed that synergistically combines memristor-based implication (IMP) logic and not-implication (N-IMP) primitives. By systematically analyzing their mapping and scheduling characteristics on circuit netlists

three cooperative strategies are introduced during the process of technology-independent optimization: optimization for rewriting the minimal-substructure

disjunctive/conjunctive duality selection for multiplexers

and collective refactoring of multi-fan-out clusters. The proposed methods achieve high-performance graph topology transformation and scheduling. Experimental results show that

compared with ABC tool

the proposed methods achieve the reduction of number of nodes after mapping by 17.32%. Furthermore

the proposed methods achieve the improvement in area overhead by 61.5% during the process of scheduling

when compared with the state-of-the-art work (AND-OR) .

关键词

Keywords

references

LIU Y, TIAN H, WU F, et al . Cellular automata imbedded memristor-based recirculated logic in-memory computing[J ] . Nature Communication, 2023, 14: 2695.

KUANG X Y, HUAN X L, XIAO H B, et al . Design of combinational logic circuit using multi-terminal memristor[J ] . Electronic Components and Materials, 2024, 43(8): 1024-1030.

YAN M, DONG G, XIAO Y, et al . Exact synthesis and inversion optimization for 3-input resistive majority based logic-in-memory[C ] //2024 2nd International Symposium of Electronics Design Automation (ISEDA) . Xi'an: IEEE, 2024: 266-271.

RASHED M R H, JHA S K, YAO F, et al . Hybrid digital-digital in-memory computing[C ] //2022 Design, Automation Test in Europe Conference Exhibition (DATE) . Munich: IEEE, 2022: 1177-1180.

RASHED M R H, THIJSSEN S, JHA S K, et al . STREAM: toward read-based in-memory computing for streaming-based processing for data-intensive applications[J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42(11): 3854-3867.

HAJ-ALI A, BEN-HUR R, WALD N, et al . Imaging: in-memory algorithms for image processing[J ] . IEEE Transactio ns on Circuits and Systems I: Regular Papers, 2018, 65(12): 4258-4271.

WANG F, LUO G, SUN G, et al . STAR: synthesis of stateful logic in RRAM targeting high area utilization[J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021, 40(5): 864-877.

YAO L, LIU P, WU J, et al . Integrating two logics into one crossbar array for logic gate design[J ] . IEEE Transactions on Circuits and Systems II: Express Briefs, 2021, 68(8): 2987-2991.

CHU Z F, WANG L Y, XIA Y S. Research progress of logic synthesis based on multi-logic domain[J]. Micro/nano Electronics and Intelligent Manufacturing, 2021, 3(2): 64-73.

LI Y, LIU M, REN H, et al . DAG-aware synthesis orchestration[J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024, 43(12): 4666-4675.

KVATINSKY S, SATAT G, WALD N, et al . Memristor-based material implication (IMPLY) logic: design principles and methodologies[J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013, 22(10): 2054-2066.

CHEN Q, WANG X, WA N H, et al . A logic circuit design for perfecting memristor-based material implication[J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016, 36(2): 279-284.

STRUKOV D B, SNIDER G S, STEWART D R, et al . The missing memristor found[J ] . Nature, 2008, 53(7191): 80-83.

KVATINSKY S, BELOUSOV D, LIMAN S, et al . MAGIC—memristor-aided logic[J ] . IEEE Transactions on Circuits and Systems II: Express Briefs, 2014, 61(11): 895-899.

PELED N, BEN-HUR R, RONEN R, et al . X-MAGIC: enhancing PIM using input overwriting capabilities[C ] // IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC). Salt Lake City: IFIP/IEEE, 2020: 64-69.

MURGAI R. Technology-dependent logic optimization[J]. Proceedings of the IEEE, 2015, 103(11): 2004-2020.

BEN-HUR R, RONEN R, HAJ-ALI A, et al . SIMPLER MAGIC: synthesis and mapping of in-memory logic executed in a single row to improve throughput[J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020, 39(10): 2434-2447.

RASHED M R H, THIJSSEN S, JHA S K. Logic synthesis for digital in-memory computing[C]//2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD) . San Diego: ACM/IEEE, 2022: 1-9.

ZHAO A N, XU N, LIU K, et al . The synthesis of multiple stateful logic gates for in-memory computing with low wear[J ] . Journal of Computer Research and Development, 2025, 62(3): 620-632.

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