
1. 广东工业大学 集成电路学院,广东,广州,510006
2. 牛芯半导体(深圳) 有限公司,广东,深圳,518000
Published:2025
移动端阅览
熊晓明, 詹瑞典, 饶博, 等. 我国集成电路关键技术挑战与协同创新路径[J]. 广东工业大学学报, 2025, 42(6): 1–11.
Xiong Xiaoming, Zhan Ruidian, Rao Bo, et al. Key Technological Challenges and Collaborative Innovation Pathways of China's Integrated Circuits[J]. 2025, 42(6): 1-11.
熊晓明, 詹瑞典, 饶博, 等. 我国集成电路关键技术挑战与协同创新路径[J]. 广东工业大学学报, 2025, 42(6): 1–11. DOI: 10.12052/gdutxb.250119
Xiong Xiaoming, Zhan Ruidian, Rao Bo, et al. Key Technological Challenges and Collaborative Innovation Pathways of China's Integrated Circuits[J]. 2025, 42(6): 1-11. DOI: 10.12052/gdutxb.250119.
在全球科技博弈加剧、关键技术受限的背景下,集成电路产业已成为国家战略安全和科技自主的核心领域。本文系统梳理了我国集成电路产业链发展现状,聚焦设计、制造、电子设计自动化(Electronic Design Automation,EDA)、封装等关键环节的技术瓶颈与“卡脖子”问题。在分析美国主导的技术封锁及全球产业重构趋势基础上,指出我国面临的外部压力与内生短板并存的复杂局势。结合在人工智能(Artificial Intelligence,AI)硬件加速器、软硬件协同设计、器件建模与仿真、AI辅助EDA等方面的最新研究实践,本文提出一种协同创新驱动的技术突围路径,探索后摩尔时代的算力架构、系统封装和EDA协同设计方向。最后,建议加强“工艺—器件—架构—工具—系统”一体化战略布局,建立开放可控、自主完整的技术生态体系。本文为集成电路领域的技术创新与政策制定提供理论支持和实践参考。
Against the backdrop of intensified global technological rivalry and restrictions on critical technologies
the Integrated Circuit (IC) industry has become central domain of national strategic security and technological self-reliance. This paper systematically reviews the development status of China's IC industry chain
focusing on key bottlenecks in design
manufacturing
Electronic Design Automation (EDA) tools
and advanced packaging. Based on an analysis of external pressures such as U.S.-led technology embargoes and internal structural weaknesses
the authors identify the dual challenges faced by the industry. Combined with the latest research practice in Artificial Intelligence (AI) hardware accelerators
hardware/software co-design
device modeling and simulation
and AI-assisted EDA
this paper proposes a technology breakthrough path driven by collaborative innovation
and explores new directions in computing architecture
system packaging
and EDA design under the post-Moore paradigm. This paper provides theoretical support and practical references for technological innovation and policy formulation in the integrated circuit field.
XUE L, WEI S J, LI Y, et al . The CHIPS and science act of US and analysis of its impacts[J ] . International Economic Review, 2022(6): 9-44.
XIAO Y F. The impact of the US-China trade war on China’s semiconductor industry[C] //Proceedings of the 2022 2nd International Conference on Financial Management and Economic Transition (FMET) . Shenzhen: Atlantis Press, 2022: 665-677.
龚梅芝, 陆斐. 新形势下我国集成电路产业现状及发展思考[J]. 中国集成电路, 2024, 33(Z1): 14-18.
LIANG Y, ZHUO C, LI Y F. The shift-left design paradigm of EDA: progress and challenges[J]. Scientia Sinica(Informationis) , 2024, 54(1): 121-129.
KANG W, KOU J, ZHAO W S. In-memory computing technology: development status, trends and challenges[J]. Scientia Sinica(Informationis) , 2024, 54(1): 16-24.
YE L, JIA T Y, CHEN P Y, et al . SRAM-based compute-in-memory: status and challenges[J ] . Scientia Sinica(Informationis) , 2024, 54(1): 25-33.
LIU W Q, CHEN K, WU B, et al . High-efficiency and high-security emerging computing chips: development, challenges, and prospects[J ] . Scientia Sinica(Informationis) , 2024, 54(1): 34-47.
CHEN Y J, CAI Y M, WANG Y, et al . Integrated circuit technology: future development and key issues–review of the 347th “Shuangqing Forum(Youth) ”[J ] . Scientia Sinica(Informationis) , 2024, 54(1): 1-5.
WANG Y, ZHANG L, ZHANG W. The development and application of artificial intelligence chips[C]//2022 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA) . Dalian: IEEE, 2022: 689-696.
ZHENG X, LIANG S Z, XIONG X M. A hardware/software partitioning method based on graph convolutional network[J]. Design Automation for Embedded Systems, 2021, 25(4): 325-351.
ZHENG X, WU J W, LIN X, et al . Hardware/software co-design of cryptographic SoC based on RISC-V virtual prototype[J ] . IEEE Transactions on Circuits and Systems II: Express Briefs, 2023, 70(9): 3624-3628.
LYULYAVA D, DUKSIN N, DUKSINA I, et al . Organization of an automated design flow for FPGA and ASIC[C ] // Proceedings of the 6th International Conference on Control Systems, Mathematical Modeling, Automation and Energy Efficiency (SUMMA) . Lipetsk: IEEE, 2024: 1107-1110.
ROMASZKAN W, LI T, GARG R, et al . A 4.4-75-TOPS/W 14-nm programmable, performance- and precision-tunable all-digital stochastic computing neural network inference accelerator[J ] . IEEE Solid-State Circuits Letters, 2022, 5: 206-209.
CHEN Z, MA Y, WANG Z. Hybrid stochastic-binary computing for low-latency and high-precision inference of CNNs[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2022, 69(7): 2707-2720.
ARMENIAKOS G, ZERVAKIS G, SOUDRIS D, et al . Hardware approximate techniques for deep neural network accelerators: a survey[J ] . ACM Computing Surveys, 2022, 55(4): 1-36.
ZHANG Y, WANG R, JIANG X, et al . Design guidelines of stochastic computing based on FinFET: a t echnology-circuit perspective[C ] //2017 IEEE International Electron Devices Meeting (IEDM) . San Francisco: IEEE, 2017: 6.6. 1-6.6. 4.
XUE C X, HUNG J M, KAO H Y, et al . 16.1 A 22 nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices[C ] //2021 IEEE International Solid-State Circuits Conference (ISSCC) . San Francisco: IEEE, 2021, 64: 245-247.
SUN X, KHWA W S, CHEN Y S, et al . PCM-based analog compute-in-memory: impact of device non-idealities on inference accuracy[J ] . IEEE Transactions on Electron Devices, 2021, 68(11): 5585-5591.
AMROUCH H, IMANI M, JIAO X, et al . Brain-inspired hyperdimensional computing for ultra-efficient edge AI[C ] //2022 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS) . Shanghai: IEEE, 2022: 25-34.
MEHTA R. Advancing graph processing: a hardware-software co-design approach[J]. International Journal of Computer Science Information System, 2025, 10(5): 1-6.
GUO C, CHENG F, DU Z, et al . A survey: collaborative hardware and software design in the era of large language models[J ] . IEEE Circuits and Systems Magazine, 2025, 25(1): 35-57.
PENTA S, ZHENG T, TREMBLE E, et al . Performance evaluation of ucie-based die-to-die interface on low-cost 2d packaging technology[C ] //2024 IEEE 74th Electronic Components and Technology Conference (ECTC) . Denver: IEEE, 2024: 274-278.
HE W, YIN E, ZHOU F, et al . Integrated manifold microchannels and near-junction cooling for enhanced thermal management in 3D heterogeneous packaging technology[J ] . Energy, 2024, 305: 132263.
SUN Q, CHEN T, LIU S, et al . Correlated multi-objective multi-fidelity optimization for HLS directives design[J ] . ACM Transactions on Design Automation of Electronic Systems (TODAES) , 2022, 27(4): 1-27.
JIA X, WANG J, CAI Y, et al . Electromigration design rule aware global and detailed routing algorithm[C ] //Proceedings of the 2018 Great Lakes Symposium on VLSI (GLSVLSI) . Chicago: ACM, 2018: 267-272.
MA X, WANG Z, CHEN X, et al . Gradient-based source mask optimization for extreme ultraviolet lithography[J ] . IEEE Transactions on Computational Imaging, 2018, 5(1): 120-135.
CHAI Z, ZHAO Y, LIU W, et al . Circuitnet : an open-source dataset for machine learning in VLSI cad applications with improved domain-specific evaluation metric and learning strategies[J ] . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023, 42(12): 5034-5047.
HU X H, LI X M, HUANG H M, et al . TiNNA: a tiny accelerator for neural networks with efficient DSP optimization[J ] . IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(4): 2301-2305.
HU X H, HUANG H M, LI X M, et al . High-performance reconfigurable DNN accelerator on a bandwidth-limited embedded system[J ] . ACM Transactions on Embedded Computing Systems, 2023, 22(6): 1-20.
ZHENG X, ZENG S, ZHONG Y, et al . An efficient VCD parser for dynamic power estimation of digital integrated circuits[J ] . IEEE Embedded Systems Letters, 2024, 16(4): 461-464.
LI L, GUNTER E L. K-LLVM: a relatively complete semantics of LLVM IR[C] //34th European Conference on Object-Oriented Programming (ECOOP) . Berlin: Dagstuhl, 2020: 7: 1-7: 29.
WANG X, WEI Y, XIONG Y, et al . Lightseq2: accelerated training for transformer-based models on gpus[C ] //International Conference for High Performance Computing, Networking, Storage, and Analysis (SC22) . D allas: IEEE, 2022: 1-14.
KININGHAM K, LEVIS P, RÉ C. GRIP: a graph neural network accelerator architecture[J]. IEEE Transactions on Computers, 2022, 72(4): 914-925.
PEI J, DENG L, SONG S, et al . Towards artificial general intelligence with hybrid Tianjic chip architecture[J ] . Nature, 2019, 572(7767): 106-111.
TIAN K K, JIANG Y, LI W J, et al . Size-dependent competitive effect between surface recombination and self-heat on efficiency droop for 250 nm AlGaN-based DUV LEDs[J ] . Optics Letters, 2024, 49(22): 6369-6372.
YANG J Y, TIAN K K, CHU C S, et al . Design and optimization for AlGaN-based deep ultraviolet fabry-perot laser diodes[J ] . Advanced Electronic Materials, 2025, 11(1): 2400247.
YU F, DENG W L, HUANG J K, et al . An explicit physics-based I-V model for surrounding-gate polysilicon transistors[J ] . IEEE Transactions on Electron Devices, 2016, 63(3): 1059-1065.
GU H, ZHENG X, WANG Y, et al . Multiscale feature attention and transformer based congestion prediction for routability-driven FPGA macro placement[C ] // 2025 Design, Automation Test in Europe Conference (DATE) . Lyon: IEEE, 2025: 1-7.
DING M, GUO Y, HUANG Z, et al . GROM: a generalized routing optimization method with graph neural network and deep reinforcement learning[J ] . Journal of Network and Computer Applications, 2024, 229: 103927.
ZHENG X, CHENG M J, CHEN J S, et al . BSSE: design space exploration on the BOOM with semi-supervised learning[J ] . IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024, 32(5): 860-869.
MO G Q, XIA Y M, OU J H, et al . Layout congestion prediction based on Regression-ViT[J ] . ACM Transactions on Design Automation of Electronic Systems, 2024, 30(1): 1-21.
FANG W J, GUO L K, LIN J W, et al . Obstacle-aware length-matching routing for any-direction traces in printed circuit board[C ] //In Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC) . San Francisco: IEEE, 2024 : 1-6.
LIN W X, WU H J, GAO P, et al . Sequential pouting-based time-division multiplexing optimization for multi-FPGA systems[J ] . ACM Transactions on Design Automation of Electronic Systems, 2023, 28(6): 1-10.
VERMA P. DSO AI-a distributed system to optimize physical design flows[C] //Proceedings of the 2024 International Symposium on Physical Design (ISPD) . Taiwan: ACM, 2024: 115-116.
0
Views
0
下载量
0
CSCD
Publicity Resources
Related Articles
Related Author
Related Institution
京公网安备11010802024621