A Design of High-efficiency Class E Power Amplifier Based on GaAs pHEMT Process

Liu Ke; Zeng Linqi; Ye Zhicong; Zhang Zhihao; Zhang Guohao

doi:10.12052/gdutxb.250094

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A Design of High-efficiency Class E Power Amplifier Based on GaAs pHEMT Process

更新时间：2026-05-27

- A Design of High-efficiency Class E Power Amplifier Based on GaAs pHEMT Process
- Vol. 42, Issue 6, Pages: 18-26(2025)
- 作者机构：
  
  广东工业大学集成电路学院,广东,广州,510006
- 作者简介：
- 基金信息：
- DOI：10.12052/gdutxb.250094
  CLC： TN722
- Published：2025
- 稿件说明：
移动端阅览
刘柯, 曾琳淇, 叶志聪, 等. 一种基于GaAs pHEMT工艺的高效率E类功率放大器设计[J]. 广东工业大学学报, 2025, 42(6): 18–26.

Liu Ke, Zeng Linqi, Ye Zhicong, et al. A Design of High-efficiency Class E Power Amplifier Based on GaAs pHEMT Process[J]. 2025, 42(6): 18-26.
刘柯, 曾琳淇, 叶志聪, 等. 一种基于GaAs pHEMT工艺的高效率E类功率放大器设计[J]. 广东工业大学学报, 2025, 42(6): 18–26. DOI： 10.12052/gdutxb.250094

Liu Ke, Zeng Linqi, Ye Zhicong, et al. A Design of High-efficiency Class E Power Amplifier Based on GaAs pHEMT Process[J]. 2025, 42(6): 18-26. DOI： 10.12052/gdutxb.250094.

摘要

针对5G Sub-6 GHz通信系统对S波段(2~4 GHz)射频功率放大器(Power Amplifier

PA)在高效率、高线性度及宽带性能方面的迫切需求，本文提出了一种基于砷化镓赝配高电子迁移率晶体管(Gallium Arsenide Pseudomorphic High Electron Mobility Transistor

GaAs pHEMT)工艺的创新设计。传统硅基CMOS工艺在高频场景中受限于击穿电压与寄生效应，而氮化镓(GaN)工艺因成本与集成度问题难以广泛应用。因此，研究聚焦于GaAs pHEMT工艺的潜力，旨在通过优化谐波抑制与阻抗匹配网络，突破S波段PA在效率、带宽及谐波抑制方面的技术瓶颈，同时探索其在射频前端模组中的集成应用。研究采用混合π型谐波匹配网络与电抗补偿技术，通过单级拓扑结构集成阻抗变换、谐波抑制及寄生参数动态补偿功能，解决了传统多级LC网络带宽受限(10%)与面积冗余的难题。设计结合片外分立LC补偿模块，优化高频寄生效应，并采用两级级联架构(驱动级与功率级)提升增益与功率输出。通过精确调谐栅极(0.38 V/0.45 V)与漏极(6 V)偏置电压，结合版图对称布局与电磁仿真优化，显著降低非线性失真与直流功耗。实验结果表明，所设计的E类功率放大器在2.45~2.85 GHz频段内实现15%的相对带宽，二次谐波抑制比优于20 dB(5.3 GHz处)，负载阻抗优化至50 Ω。实测功率附加效率(Power Added Efficiency

PAE)在中心频率2.65 GHz时达到56.4%，输出功率为26.2 dBm，增益为26 dB，综合性能优于同类研究。

Abstract

To address the urgent demand for high-efficiency

high-linearity

and broadband performance in S-band (2~4 GHz) radio frequency power amplifiers (PAs) for 5G Sub-6 GHz communication systems

an innovative design is proposed based on Gallium Arsenide Pseudomorphic High Electron Mobility Transistor (GaAs pHEMT) technology. Traditional silicon-based CMOS processes faced limitations in high-frequency scenarios due to breakdown voltage and parasitic effects

while Gallium Nitride (GaN) technology struggled with cost and integration challenges. The research focused on leveraging the potential of GaAs pHEMT technology to overcome efficiency

bandwidth

and harmonic suppression bottlenecks in S-band PAs and explored its integration in radio frequency front-end modules. The study employed a hybrid π-shaped harmonic matching network combined with reactance compensation technology. A single-stage topology integrated impedance transformation

harmonic suppression

and dynamic parasitic parameter compensation

resolving the limitations of traditional multi-stage LC networks (bandwidth 10%) and excessive area occupation. Off-chip discrete LC compensation modules were introduced to optimize high-frequency parasitic effects

and a two-stage cascaded architecture (driver stage and power stage) enhanced gain and power output. By precisely tuning gate (0.38 V/0.45 V) and drain (6 V) bias voltages

along with symmetric layout design and electromagnetic simulation optimization

nonlinear distortion and DC power consumption were significantly reduced. Experimental results demonstrate that the designed Class-E PA achieves a 15% fractional bandwidth in the 2.45~2.85 GHz range

with a second harmonic suppression ratio exceeding 20 dB (at 5.3 GHz) and optimized load impedance of 50 Ω. The measured power-added efficiency (PAE) reaches 56.4% at the center frequency of 2.65 GHz

with an output power of 26.2 dBm and a gain of 26 dB

outperforming existing solutions.

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Keywords

references

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