A Design of a 24-27 GHz Cascode High Gain Low Noise Amplifier

Chen Hong-qi; Luo De-xin; Lan Liang; Zhang Zhi-hao; Zhang Guo-hao

doi:10.12052/gdutxb.240115

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A Design of a 24-27 GHz Cascode High Gain Low Noise Amplifier

更新时间：2026-05-27

- A Design of a 24-27 GHz Cascode High Gain Low Noise Amplifier
- Vol. 41, Issue 6, Pages: 26-32(2024)
- 作者机构：
  
  1. 广东工业大学信息工程学院,广东,广州,510006
  2. 广东工业大学集成电路学院,广东,广州,510006
- 作者简介：
- 基金信息：
- DOI：10.12052/gdutxb.240115
  CLC： TN492
- Published：2024
- 稿件说明：
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陈鸿棋, 罗德鑫, 蓝亮, 张志浩, 章国豪. 一种24~27 GHz共源共栅高增益低噪声放大器设计[J]. 广东工业大学学报, 2024, 41(6): 26-32.

Chen Hong-qi, Luo De-xin, Lan Liang, et al. A Design of a 24-27 GHz Cascode High Gain Low Noise Amplifier[J]. 2024, 41(6): 26-32.
陈鸿棋, 罗德鑫, 蓝亮, 张志浩, 章国豪. 一种24~27 GHz共源共栅高增益低噪声放大器设计[J]. 广东工业大学学报, 2024, 41(6): 26-32. DOI： 10.12052/gdutxb.240115.

Chen Hong-qi, Luo De-xin, Lan Liang, et al. A Design of a 24-27 GHz Cascode High Gain Low Noise Amplifier[J]. 2024, 41(6): 26-32. DOI： 10.12052/gdutxb.240115.

摘要

基于40 nm CMOS工艺，设计了一款高增益的低噪声放大器芯片。该芯片的拓扑架构采用了变压器输入匹配技术和正反馈同相放大技术，以提高输入匹配程度和增益。通过在传统共源共栅结构的输入级引入有源偏置网络及变压器匹配网络，实现的芯片在仿真环境下不仅能够在常温条件下稳定工作，还展现出−40 ℃~125 ℃范围内的优越性能。因此，该设计可用于不同温度环境下毫米波频段的收发机接收端口，并且有着一定的温度稳定特性。该低噪声放大器芯片的版图尺寸为0.383 mm×0.694 mm。版图后仿真结果显示，在24~27 GHz的工作频段内，该低噪声放大器常温下实现了低于4.96 dB的噪声系数、18.11 dB的最大增益、小于−16.08 dB的输入回波损耗和小于−11.54 dB的输出回波损耗。此外，该低噪声放大器设计还具有输入

1dB

为−20.36 dBm、直流功耗

diss

为12.8 mW等优异指标。

Abstract

Based on a 40 nm CMOS process

a high-gain low noise amplifier (LNA) chip was designed. The topology architecture of the chip adopted transformer input matching technology and positive feedback same-phase amplification technology to improve the input matching degree and gain. By introducing an active biasing network and a transformer matching network into the input stage of the traditional common-source common-gate structure

the chip can not only work stably at room temperature

but also shows excellent performance within the temperature range of −40 ℃ to 125 ℃ in simulat

ion. Therefore

this design can be used for transceiver receiving ports in millimeter wave frequency bands under different temperature environments

and has certain temperature stability characteristics. The chip’s layout size is 0.383 mm×0.694 mm. The post-layout simulation results show that the LNA achieves a noise figure of less than 4.96 dB

a maximum gain of 18.11 dB

an input return loss of less than −16.08 dB

and an output return loss of less than −11.54 dB within the working frequency range of 24~27 GHz at room temperature. In addition

the LNA design has excellent performance indicators such as an input

1dB

of −20.36 dBm and a DC power dissipation of 12.8 mW.

关键词

Keywords

references

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