DC Fault Current Analytical Calculation of MMC-HVDC System Including Fault Current Limiter

The rapid rise of the fault current brings about great challenges to the protection of the system when a DC short circuit fault occurs in a high voltage direct current system based on modular multilevel converters (MMC-HVDC). Usually, the fault current limiters (FCL) are installed at both the ends of the DC line to suppress the fault current for a half-bridge-based MMC-HVDC system. When optimizing the design of FCL and performing the fault protection, the calculation of the fault current including the FCL input is of great significance. In this paper, an equivalent transient model of the impedance-based FCL in the action stage is derived in terms of the characteristics of the metal oxide arrester (MOA), in which the evolution of the fault current after a fault is divided into three stages. The analytical expressions of the fault current in the three stages are derived respectively, and the analytical expression of the fault current in the whole process is obtained. The electromagnetic transient model for a double-terminal MMC-HVDC system built in PSCAD/EMTDC is used to verify the analysis results. The simulation results show that the maximum deviation is smaller than 3.5% between the analysis results and the simulation results within 10ms after the fault, which meets the actual engineering application needs.