一种适用于谐振式DAB拓扑的桥口脉冲ZVS优化方法

A Bridge Pulse-ZVS Optimization Method for Resonant DAB Topology

  • 摘要: 本文以CLLC谐振式DAB拓扑为例,通过对拓扑工作机理的分析,设计出一种可有效优化由于控制电路杂散及驱动信号误差等原因所导致的拓扑全负载范围内ZVS(Zero Voltage Switch,零电压开关)实现困难的方法。方法中所包含的可调驱动板上设计有电位器Radj,通过Radj可对驱动核MOD管脚对GND间电阻阻值进行精确调整,即对IGBT模块死区时间进行精确调整。进一步的,通过模块脉冲对齐测试电路可对隔离变压器同名端两侧的IGBT半桥进行驱动脉冲对齐,且通过抖动居中的方式,减小死区时间抖动所带来的误差,帮助拓扑实现全负载范围下ZVS工作,提升拓扑的工作效率。

     

    Abstract: Taking CLLC resonant DAB topology as an example, through the analysis of the working mechanism of this type of topology, this paper designs a method that can effectively reduce the difficulty of ZVS (Zero Voltage Switch) implementation in the full load range of this type of topology caused by the stray parameter of control circuit and the deviation of the driving signal. The adjustable drive board included in the method is designed with a potentiometer Radj. Through Radj, the resistance value between GND and the MOD pin of the drive core can be accurately adjusted, that is, the dead time of the IGBT module can be accurately adjusted. Further, the module pulse alignment test circuit can align the drive pulses of IGBT half bridges on both sides of dotted terminal of isolating transformer, and reduce the deviation caused by dead time jitter by centering the jitter, realize ZVS operation under full load range and improve the working efficiency of resonant DAB topology.

     

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